From b5e4e3441841d8d1b7fac1240b7c73d288df66d5 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Wed, 30 Sep 2020 10:27:01 +0530 Subject: mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature Update TSR1 passive trip temperature BUG=b:169691800 BRANCH=None TEST=Built and tested on dedede system Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index fa10152a4e..715da7aaa2 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -75,7 +75,7 @@ chip soc/intel/jasperlake register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)" register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000)" register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)" register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)" -- cgit v1.2.3