From b5df56f6f20d075a86267cc3a00f2ff818ea1bc2 Mon Sep 17 00:00:00 2001 From: Varshit Pandya Date: Mon, 18 Jan 2021 09:44:35 +0530 Subject: soc/intel/alderlake: Adding Kconfig for ADL_M PCH 1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig 2. Select number of I/O based on PCH Signed-off-by: Varshit Pandya Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630 Reviewed-by: Subrata Banik Reviewed-by: Rizwan Qureshi Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 8009a42ae1..e7d37fb953 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -3,6 +3,11 @@ config SOC_INTEL_ALDERLAKE help Intel Alderlake support +config SOC_INTEL_ALDERLAKE_PCH_M + bool + help + Choose this option if you have PCH-M chipset. + if SOC_INTEL_ALDERLAKE config CPU_SPECIFIC_OPTIONS @@ -121,10 +126,12 @@ config HEAP_SIZE config MAX_PCH_ROOT_PORTS int + default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 config MAX_CPU_ROOT_PORTS int + default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 3 config MAX_ROOT_PORTS @@ -133,6 +140,7 @@ config MAX_ROOT_PORTS config MAX_PCIE_CLOCKS int + default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 config SMM_TSEG_SIZE -- cgit v1.2.3