From af92d07503600695df44f59aa7c8f9c19b4e462d Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 14 Mar 2022 15:08:27 +0800 Subject: mb/google/brya: Remove mainboard.asl Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/dsdt.asl | 1 - src/mainboard/google/brya/mainboard.asl | 26 --------------- src/mainboard/google/brya/mainboard.c | 38 ++++++++++++++++++++++ .../baseboard/include/baseboard/variants.h | 7 ++++ .../baseboard/nissa/include/baseboard/gpio.h | 2 ++ 5 files changed, 47 insertions(+), 27 deletions(-) delete mode 100644 src/mainboard/google/brya/mainboard.asl diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index fed071b5d3..82cafcfbf5 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -22,7 +22,6 @@ DefinitionBlock( #include Scope (\_SB) { - #include "mainboard.asl" #if CONFIG(HAVE_WWAN_POWER_SEQUENCE) #include "wwan_power.asl" #endif diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl deleted file mode 100644 index 8ca694d152..0000000000 --- a/src/mainboard/google/brya/mainboard.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#if CONFIG(HAVE_SLP_S0_GATE) -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.PEPD._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* - * On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of - * the platform can transition to its low power state as well. - */ - \_SB.PCI0.CTXS(GPIO_SLP_S0_GATE); - } Else { - /* - * On S0ix exit, set the SLP_S0_GATE pin, so that the rest of - * the platform will resume from its low power state. - */ - \_SB.PCI0.STXS(GPIO_SLP_S0_GATE); - } -} -#endif diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 42536bb793..b3f42cae20 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include @@ -109,6 +110,23 @@ static void mainboard_generate_shutdown(const struct device *dev) } } +static void mainboard_generate_s0ix_hook(void) +{ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_ENTRY); + } + acpigen_write_else(); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_EXIT); + } + acpigen_write_if_end(); +} + static void mainboard_fill_ssdt(const struct device *dev) { const struct device *wwan = DEV_PTR(rp6_wwan); @@ -122,6 +140,13 @@ static void mainboard_fill_ssdt(const struct device *dev) } /* for variant to fill additional SSDT */ variant_fill_ssdt(dev); + + acpigen_write_scope("\\_SB"); + acpigen_write_method_serialized("MS0X", 1); + mainboard_generate_s0ix_hook(); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ + } void __weak variant_fill_ssdt(const struct device *dev) @@ -129,6 +154,19 @@ void __weak variant_fill_ssdt(const struct device *dev) /* Add board-specific SSDT entries */ } +void __weak variant_generate_s0ix_hook(enum s0ix_entry) +{ + /* Add board-specific MS0X entries */ + /* + if (s0ix_entry == S0IX_ENTRY) { + implement variant operations here + } + if (s0ix_entry == S0IX_EXIT) { + implement variant operations here + } + */ +} + static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 7c1ce21f6c..9accc08f9d 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -25,6 +25,13 @@ bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config); void variant_fill_ssdt(const struct device *dev); +enum s0ix_entry { + S0IX_EXIT, + S0IX_ENTRY, +}; + +void variant_generate_s0ix_hook(enum s0ix_entry); + /* Modify devictree settings during ramstage */ void variant_devtree_update(void); diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h index 068aaa4835..51e4b207f9 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h @@ -16,5 +16,7 @@ #define GPIO_EC_IN_RW GPP_F18 /* GPIO IRQ for tight timestamps */ #define EC_SYNC_IRQ GPD2_IRQ +/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */ +#define GPIO_SLP_S0_GATE GPP_H18 #endif /* __BASEBOARD_GPIO_H__ */ -- cgit v1.2.3