From adac4af1763b3258f68e57784ef7f5ee34c04e6a Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 23 Jul 2024 15:29:21 +0800 Subject: soc/amd/psp_verstage: Add -Oz flag for clang When we tried to add CMOS support to PSP verstage (CB:83495), the clang builds failed on boards with cezanne SoC (such as Guybrush), due to over-sized verstage. On the other hand, there is no such problem for gcc builds on the same boards. Building PSP verstage by clang generates much larger verstage size (81K) compared with using gcc (67K). To unblock adding features to verstage, temporarily enable -Oz for clang builds. Change-Id: I033458556986ade88fb8e68499b632deae4dd419 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Karthik Ramasubramanian Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber --- src/soc/amd/common/psp_verstage/Makefile.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/amd/common/psp_verstage/Makefile.mk b/src/soc/amd/common/psp_verstage/Makefile.mk index ee71d9930e..9a2cd8196e 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.mk +++ b/src/soc/amd/common/psp_verstage/Makefile.mk @@ -9,6 +9,9 @@ ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_arm += -Wstack-usage=40960 else CFLAGS_arm += -Wframe-larger-than=40960 +# Cezanne only has 148KB SRAM for PSP verstage. +# Add -Oz to reduce the verstage size for clang. +CFLAGS_arm += -Oz endif verstage-y += boot_dev.c -- cgit v1.2.3