From ad88fda1cf8ad21db47be4a212e1d6e6239d058b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 24 Jul 2013 04:06:37 -0700 Subject: exynos5420: Fix the clock divisor mask The divisor mask had been set to 0xff, but the bitfield is 4 bits wide. Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5 Signed-off-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/63188 Reviewed-by: David Hendricks Commit-Queue: Gabe Black Tested-by: Gabe Black Reviewed-on: http://review.coreboot.org/4384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/samsung/exynos5420/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index b75540e099..11e46d1b52 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -359,7 +359,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned shift; - unsigned mask = 0xff; + unsigned mask = 0xf; u32 *reg; switch (periph_id) { -- cgit v1.2.3