From ac8c357ddcf2c58c4903c198224b13f045672ca4 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 27 Jan 2021 12:50:06 +0530 Subject: mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics 1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/mainboard/intel/adlrvp/gpio.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 3131cc0c05..1996683778 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -226,10 +226,9 @@ static const struct pad_config gpio_table[] = { /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* SATADevSlpPin to GPIO pin mapping */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* SATA DIRECT DEVSLP*/ - PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + /* SATA DEVSLP */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), /* SATA LED pin */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -- cgit v1.2.3