From ac6565279ce30e2eed8e5fcc14f687013717c82f Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Thu, 5 Nov 2020 22:20:52 +0000 Subject: soc/intel/skylake: Enable PCH thermal depending on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/mainboard/protectli/vault_kbl/ramstage.c | 1 - src/soc/intel/skylake/chip.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 962702fb5a..9518b1d721 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -13,7 +13,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->TurboMode = 1; - params->PchThermalDeviceEnable = 0; params->PchPort61hEnable = 1; params->CdClock = 3; } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 89eaef5b56..1e13428252 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -295,6 +295,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(SA_DEVFN_TS); params->Device4Enable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + params->PchThermalDeviceEnable = dev && dev->enabled; params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; -- cgit v1.2.3