From a9e4567c4b0dead27bcd3ed3044931eb5d81bec1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 8 Aug 2023 01:56:06 +0200 Subject: soc/amd/glinda/include/data_fabric: add DF PCI config map register PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference. Signed-off-by: Felix Held Change-Id: Ie54fd6c5a82f368018d0b5fb811a6c9220c2c70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77079 Reviewed-by: Martin L Roth Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/include/soc/data_fabric.h | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 9e7a2f475a..345702f460 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -8,6 +8,37 @@ #define IOMS0_FABRIC_ID 15 +#define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) +#define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) + +#define DF_PCI_CFG_MAP_COUNT 8 + +#define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) +#define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) +#define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) + +union df_pci_cfg_base { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 6; /* [ 2.. 7] */ + uint32_t segment_num : 8; /* [ 8..15] */ + uint32_t bus_num_base : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + +union df_pci_cfg_limit { + struct { + uint32_t dst_fabric_id : 6; /* [ 0.. 5] */ + uint32_t : 10; /* [ 6..15] */ + uint32_t bus_num_limit : 8; /* [16..23] */ + uint32_t : 8; /* [24..31] */ + }; + uint32_t raw; +}; + #define DF_IO_BASE0 DF_REG_ID(0, 0xd00) #define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04) -- cgit v1.2.3