From a8b35be75e51b35c52ea8f427155cb98aeecfc61 Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Tue, 25 Jul 2017 14:11:31 -0400 Subject: purism/librem13v2: Fix USB settings and set OC pin The USB settings were wrong in some places, or missing and the USB_OC values were taken from the schematics. Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a Signed-off-by: Youness Alaoui Reviewed-on: https://review.coreboot.org/22043 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Martin Roth --- src/mainboard/purism/librem13v2/devicetree.cb | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 76a0f7ebaf..17c764bb1d 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -154,14 +154,17 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port # PL2 override 25W -- cgit v1.2.3