From a88d5e3bcafdbc8d2cc2491a04de839eef4f6a4e Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 15 Sep 2022 08:06:49 +0530 Subject: mb/intel/adlrvp_n: Disable the External 1.05v VR in S0 Disable the external 1.05v VR in S0 as a fix for the display flicker issue in ADL-N. Please refer the Doc with ID 742988 for more details. BUG=b:248249033, b:245970842 TEST=Verified that the display flicker issue is fixed. Signed-off-by: V Sowmya Change-Id: If9f40e6c37e80caceb726a8e5f4d4b14dc479858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67654 Reviewed-by: Vidya Gopalakrishnan Tested-by: build bot (Jenkins) Reviewed-by: Reka Norman Reviewed-by: Angel Pons Reviewed-by: Kangheui Won --- src/mainboard/intel/adlrvp/devicetree_n.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index ae9e11ec9b..b54a134530 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -138,7 +138,7 @@ chip soc/intel/alderlake # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, -- cgit v1.2.3