From a69a687ec72f453f5ccacc98fece659e8aad803f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 15:20:31 +0200 Subject: sb/intel/i82801ix/Makefile.inc: Sort entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42649 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801ix/Makefile.inc | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 5844b91838..91ac65b537 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -2,31 +2,32 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) -ramstage-y += i82801ix.c +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += dmi_setup.c +romstage-y += early_init.c +romstage-y += early_smbus.c + ramstage-y += fadt.c -ramstage-y += pci.c +ramstage-y += hdaudio.c +ramstage-y += i82801ix.c ramstage-y += lpc.c +ramstage-y += pci.c ramstage-y += pcie.c -ramstage-y += usb_ehci.c ramstage-y += sata.c -ramstage-y += hdaudio.c -ramstage-y += thermal.c ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c +smm-y += smihandler.c + ifeq ($(CONFIG_SMM_ASEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif -smm-y += smihandler.c - -bootblock-y += bootblock.c -bootblock-y += early_init.c - -romstage-y += early_init.c -romstage-y += early_smbus.c -romstage-y += dmi_setup.c endif -- cgit v1.2.3