From a66b816675fc299e03092ef8d7b2c59f04641fb7 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 21 Apr 2021 10:48:20 -0700 Subject: soc/intel/jasperlake: Remove TCSS setting from the DMAR table The Jasperlake does not support TCSS. This change removes the TCSS setting from the DMAR table. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao Change-Id: I573e2038fd76ac66af88125117774b40cc80c704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/acpi.c | 14 -------------- src/soc/intel/jasperlake/include/soc/iomap.h | 12 ------------ src/soc/intel/jasperlake/include/soc/systemagent.h | 10 ---------- 3 files changed, 36 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index ebfa6685fe..f73766a8d7 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -216,20 +216,6 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - /* TCSS Thunderbolt root ports */ - for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { - uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK; - bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED; - if (tbtbar && tbten) { - unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci(current, 0, 7, i); - - acpi_dmar_drhd_fixup(tmp, current); - } - } - /* Add RMRR entry */ const unsigned long tmp = current; current += acpi_create_dmar_rmrr(current, 0, diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index eece24aa96..a6ac8367a3 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -29,18 +29,6 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 -#define TBT0_BASE_ADDRESS 0xfed84000 -#define TBT0_BASE_SIZE 0x1000 - -#define TBT1_BASE_ADDRESS 0xfed85000 -#define TBT1_BASE_SIZE 0x1000 - -#define TBT2_BASE_ADDRESS 0xfed86000 -#define TBT2_BASE_SIZE 0x1000 - -#define TBT3_BASE_ADDRESS 0xfed87000 -#define TBT3_BASE_SIZE 0x1000 - #define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_SIZE 0x1000 diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 6acd7f3e4b..d6f41257a5 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -24,12 +24,6 @@ #define IMRBASE 0x6a40 #define IMRLIMIT 0x6a48 #define IPUVTBAR 0x7880 -#define TBT0BAR 0x7888 -#define TBT1BAR 0x7890 -#define TBT2BAR 0x7898 -#define TBT3BAR 0x78a0 - -#define MAX_TBT_PCIE_PORT 4 #define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull @@ -37,10 +31,6 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = { { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; -- cgit v1.2.3