From a63ce30c93c43ccbfde26e9a68e4419e4891ff7f Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Wed, 3 Apr 2024 22:57:41 +0530 Subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. This alignment is consistent for both x86_64 and x86_32 modes to simplify the implementation. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Krishna P Bhat D --- src/drivers/intel/fsp2_0/memory_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 31ae21336c..7e9676c666 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,7 +34,7 @@ void __weak platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index) /* Leave for the SoC/Mainboard to implement if necessary. */ } -static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); +static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(16); /* * Helper function to store the MRC cache version into CBMEM -- cgit v1.2.3