From a52b93b262582009decf924dbdde9bc1bf856ddb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 30 Jun 2023 18:44:26 +0300 Subject: cpu/x86: Add some notes about XAPIC/X2APIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At the time of writing SMM runtime does not make register accesses to LAPIC registers, but such breakage has been reported. S3 resume failure, where OS switched back from X2APIC to XAPIC mode, can be reproduced with a sandybridge SKU that has VT-d disabled. Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/cpu/x86/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 1e1b2ac157..4e17690cc3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -50,16 +50,26 @@ choice config XAPIC_ONLY prompt "Set XAPIC mode" bool + help + coreboot and SMM runtime only use XAPIC mode. + FIXME: DMAR should have X2APIC optout bit set. config X2APIC_ONLY prompt "Set X2APIC mode" bool depends on PARALLEL_MP + help + coreboot and SMM runtime only use X2APIC mode. + Note: OS switches back to XAPIC mode if VT-d is disabled. + FIXME: S3 resume (and SMM runtime) will break if OS makes the switch. config X2APIC_RUNTIME prompt "Support both XAPIC and X2APIC" bool depends on PARALLEL_MP + help + The switch to X2APIC mode happens early in ramstage. SMM runtime can + support either mode in case the OS switches back to XAPIC. config X2APIC_LATE_WORKAROUND prompt "Use XAPIC for AP bringup, then change to X2APIC" -- cgit v1.2.3