From a4542990f4cd5d9a18e8b0846b54fcfe5cbd01e5 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 16 Aug 2019 12:20:01 +0530 Subject: mb/google/hatch: Skip SD card controller WP pin configuration from FSP BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c87a8bcfe7..8b5fc1a403 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -46,6 +46,8 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # SD card WP pin confguration + register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of -- cgit v1.2.3