From a23e0c9d74b7f06738ebf28b068e1bd63f246982 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 25 Mar 2020 15:31:12 +0530 Subject: soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/dsdt.asl | 4 ++-- src/mainboard/google/dedede/romstage.c | 2 +- .../google/dedede/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/dedede/variants/baseboard/memory.c | 2 +- .../google/dedede/variants/waddledee/overridetree.cb | 2 +- .../google/dedede/variants/waddledoo/overridetree.cb | 2 +- src/mainboard/intel/jasperlake_rvp/dsdt.asl | 4 ++-- src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c | 2 +- .../variants/baseboard/include/baseboard/variants.h | 2 +- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- .../intel/jasperlake_rvp/variants/jslrvp/memory.c | 2 +- src/soc/intel/jasperlake/Kconfig | 6 +++--- src/soc/intel/jasperlake/Makefile.inc | 2 +- src/soc/intel/jasperlake/romstage/fsp_params.c | 2 +- src/soc/intel/tigerlake/Kconfig | 16 ++-------------- src/soc/intel/tigerlake/Makefile.inc | 2 +- 16 files changed, 21 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8cb9..98ef6e49cc 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -30,7 +30,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4538..f95e7aacc3 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 865d4ea73c..f030b20cec 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec661..08c3bde29f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 23db34e66c..388051afa0 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 884199c4c5..cb21c63b0f 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717b0e..ed59af6a96 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -37,7 +37,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 8858e44616..f185628df1 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -14,7 +14,7 @@ */ #include #include -#include +#include #include #include "board_id.h" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 27c645bbde..2fe7631281 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,7 @@ #define __BASEBOARD_VARIANTS_H__ #include -#include +#include #include #include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 386936eef8..41921dd46e 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 1915a1e1ff..4de66b3929 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 01d7294743..844a954996 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -1,9 +1,9 @@ -config SOC_INTEL_JASPERLAKE_COPY +config SOC_INTEL_JASPERLAKE bool help Intel Jasperlake support -if SOC_INTEL_JASPERLAKE_COPY +if SOC_INTEL_JASPERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -192,7 +192,7 @@ config FSP_FD_PATH depends on FSP_USE_REPO default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" -config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT +config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT int "Debug Consent for JSL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 29db4f3d00..4a65adc111 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y) +ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index ca7ff26a0e..d263834576 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -89,7 +89,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT; + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_DEBUG_CONSENT; /* VT-d config */ m_cfg->VtdDisable = 0; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 63bd881b71..e71586d64b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -1,22 +1,9 @@ -config SOC_INTEL_TIGERLAKE_BASE - bool - config SOC_INTEL_TIGERLAKE bool - select SOC_INTEL_TIGERLAKE_BASE - #TODO - Enable INTEL_CAR_NEM_ENHANCED - select INTEL_CAR_NEM help Intel Tigerlake support -config SOC_INTEL_JASPERLAKE - bool - select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM - help - Intel Jasperlake support - -if SOC_INTEL_TIGERLAKE_BASE +if SOC_INTEL_TIGERLAKE config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index e7169cff42..12d59b1f93 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y) +ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode -- cgit v1.2.3