From a233eb4b0a92c56e2d91a533b96bafbdf0413c9c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jan 2022 07:51:28 +0100 Subject: nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit_mrc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 0a7d1921d8..4027708617 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -429,7 +430,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][118] << 8) | (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } @@ -453,7 +454,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][118] << 8) | (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } -- cgit v1.2.3