From a16ed34638b32abe188c08f5027371658a299a1f Mon Sep 17 00:00:00 2001 From: Simon Yang Date: Tue, 6 Sep 2022 18:30:51 +0800 Subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc Missing power limit setting for Alder-Lake-N 7W soc. Document reference: 645548 and 646929 BUG=b:245440443 BRANCH=None TEST=Build FW and test on nivviks board and there is no error message "unknown SA ID: 0x4617, skipped power limits configuration." Signed-off-by: Simon Yang Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar --- src/soc/intel/alderlake/chip.h | 3 +++ src/soc/intel/alderlake/chipset.cb | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 06d1ef5ef4..4cb606622a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -30,6 +30,7 @@ enum soc_intel_alderlake_power_limits { ADL_M_282_15W_CORE, ADL_M_242_CORE, ADL_P_442_45W_CORE, + ADL_N_081_7W_CORE, ADL_N_081_15W_CORE, ADL_N_041_6W_CORE, ADL_N_021_6W_CORE, @@ -57,6 +58,7 @@ enum soc_intel_alderlake_power_limits { /* TDP values for different SKUs */ enum soc_intel_alderlake_cpu_tdps { TDP_6W = 6, + TDP_7W = 7, TDP_9W = 9, TDP_12W = 12, TDP_15W = 15, @@ -90,6 +92,7 @@ static const struct { { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, + { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W }, { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 0016ae745f..2b9d3802a5 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -48,6 +48,12 @@ chip soc/intel/alderlake .tdp_pl4 = 68, }" + register "power_limits_config[ADL_N_081_7W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 35, -- cgit v1.2.3