From a0199d8e1a96d94828b31f77e0a29a282871a76a Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 22 Jun 2017 16:14:58 +0800 Subject: rockchip/rk3399: update the ddr 200MHz frequency configuration This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3399/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 35c96bcf37..980adf5000 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -636,7 +636,7 @@ void rkclk_configure_ddr(unsigned int hz) switch (hz) { case 200*MHz: dpll_cfg = (struct pll_div) - {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}; break; case 300*MHz: dpll_cfg = (struct pll_div) -- cgit v1.2.3