From 9d0215363d710f7a3303724ad7a369e4a2dd2d36 Mon Sep 17 00:00:00 2001
From: Werner Zeh <werner.zeh@siemens.com>
Date: Fri, 19 Feb 2016 10:02:49 +0100
Subject: fsp_baytrail: Add full support for iosf access in reg_script

Add all needed functions to fsp_baytrail so that reg_script can
do full iosf access. To keep it simple, this patch synchronises
iosf access between baytrail and fsp_baytrail.

Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/include/reg_script.h                      |   5 +-
 src/lib/reg_script.c                          |  17 ++-
 src/soc/intel/fsp_baytrail/include/soc/iosf.h | 155 ++++++++++++++++++++++
 src/soc/intel/fsp_baytrail/iosf.c             | 181 ++++++++++++++++++++++++++
 4 files changed, 349 insertions(+), 9 deletions(-)

diff --git a/src/include/reg_script.h b/src/include/reg_script.h
index 691c82cc2c..60b1188b6c 100644
--- a/src/include/reg_script.h
+++ b/src/include/reg_script.h
@@ -290,7 +290,8 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
 	REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
 
 
-#if CONFIG_SOC_INTEL_BAYTRAIL
+#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
+IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)
 /*
  * IO Sideband Function
  */
@@ -310,7 +311,7 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
 	REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
 #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
 	REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
-#endif	/* CONFIG_SOC_INTEL_BAYTRAIL */
+#endif	/* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/
 
 /*
  * CPU Model Specific Register
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index bcfb6c5fbe..7f8200006e 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -26,7 +26,10 @@
 #include <cpu/x86/msr.h>
 #endif
 
-#if CONFIG_SOC_INTEL_BAYTRAIL
+#define HAS_IOSF (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
+		IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL))
+
+#if HAS_IOSF
 #include <soc/iosf.h>	/* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
 #endif
 
@@ -233,7 +236,7 @@ static void reg_script_write_res(struct reg_script_context *ctx)
 	reg_script_set_step(ctx, step);
 }
 
-#if CONFIG_SOC_INTEL_BAYTRAIL
+#if HAS_IOSF
 static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
 {
 	const struct reg_script *step = reg_script_get_step(ctx);
@@ -363,7 +366,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx)
 		break;
 	}
 }
-#endif
+#endif /* HAS_IOSF */
 
 
 static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
@@ -435,10 +438,10 @@ static uint64_t reg_script_read(struct reg_script_context *ctx)
 		return reg_script_read_res(ctx);
 	case REG_SCRIPT_TYPE_MSR:
 		return reg_script_read_msr(ctx);
-#if CONFIG_SOC_INTEL_BAYTRAIL
+#if HAS_IOSF
 	case REG_SCRIPT_TYPE_IOSF:
 		return reg_script_read_iosf(ctx);
-#endif
+#endif /* HAS_IOSF */
 	default:
 #ifndef __PRE_RAM__
 		{
@@ -478,11 +481,11 @@ static void reg_script_write(struct reg_script_context *ctx)
 	case REG_SCRIPT_TYPE_MSR:
 		reg_script_write_msr(ctx);
 		break;
-#if CONFIG_SOC_INTEL_BAYTRAIL
+#if HAS_IOSF
 	case REG_SCRIPT_TYPE_IOSF:
 		reg_script_write_iosf(ctx);
 		break;
-#endif
+#endif /* HAS_IOSF */
 	default:
 #ifndef __PRE_RAM__
 		{
diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
index 1c38884bb4..a220469cd2 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2016 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -51,6 +52,10 @@
 #define MDR_REG 0xd4
 #define MCRX_REG 0xd8
 
+uint32_t iosf_aunit_read(int reg);
+void iosf_aunit_write(int reg, uint32_t val);
+uint32_t iosf_cpu_bus_read(int reg);
+void iosf_cpu_bus_write(int reg, uint32_t val);
 uint32_t iosf_bunit_read(int reg);
 void iosf_bunit_write(int reg, uint32_t val);
 uint32_t iosf_dunit_read(int reg);
@@ -59,25 +64,120 @@ void iosf_dunit_write(int reg, uint32_t val);
 uint32_t iosf_dunit_ch0_read(int reg);
 uint32_t iosf_dunit_ch1_read(int reg);
 uint32_t iosf_punit_read(int reg);
+void iosf_punit_write(int reg, uint32_t val);
+uint32_t iosf_usbphy_read(int reg);
+void iosf_usbphy_write(int reg, uint32_t val);
+uint32_t iosf_ushphy_read(int reg);
+void iosf_ushphy_write(int reg, uint32_t val);
+uint32_t iosf_sec_read(int reg);
+void iosf_sec_write(int reg, uint32_t val);
+uint32_t iosf_port45_read(int reg);
+void iosf_port45_write(int reg, uint32_t val);
+uint32_t iosf_port46_read(int reg);
+void iosf_port46_write(int reg, uint32_t val);
+uint32_t iosf_port47_read(int reg);
+void iosf_port47_write(int reg, uint32_t val);
+uint32_t iosf_port55_read(int reg);
+void iosf_port55_write(int reg, uint32_t val);
+uint32_t iosf_port58_read(int reg);
+void iosf_port58_write(int reg, uint32_t val);
+uint32_t iosf_port59_read(int reg);
+void iosf_port59_write(int reg, uint32_t val);
+uint32_t iosf_port5a_read(int reg);
+void iosf_port5a_write(int reg, uint32_t val);
 uint32_t iosf_lpss_read(int reg);
 void iosf_lpss_write(int reg, uint32_t val);
+uint32_t iosf_ccu_read(int reg);
+void iosf_ccu_write(int reg, uint32_t val);
+uint32_t iosf_score_read(int reg);
+void iosf_score_write(int reg, uint32_t val);
+uint32_t iosf_scc_read(int reg);
+void iosf_scc_write(int reg, uint32_t val);
+uint32_t iosf_porta2_read(int reg);
+void iosf_porta2_write(int reg, uint32_t val);
+uint32_t iosf_ssus_read(int reg);
+void iosf_ssus_write(int reg, uint32_t val);
 
 /* IOSF ports. */
 #define IOSF_PORT_AUNIT		0x00 /* IO Arbiter unit */
 #define IOSF_PORT_SYSMEMC	0x01 /* System Memory Controller */
+#define IOSF_PORT_DUNIT_CH0	0x07 /* DUNIT Channel 0 */
+#define IOSF_PORT_CPU_BUS	0x02 /* CPU Bus Interface Controller */
 #define IOSF_PORT_BUNIT		0x03 /* System Memory Arbiter/Bunit */
+#define IOSF_PORT_PMC		0x04 /* Power Management Controller */
+#define IOSF_PORT_GFX		0x06 /* Graphics Adapter */
 #define IOSF_PORT_DUNIT_CH1	0x07 /* DUNIT Channel 1 */
+#define IOSF_PORT_SYSMEMIO	0x0c /* System Memory IO */
 #define IOSF_PORT_USBPHY	0x43 /* USB PHY */
+#define IOSF_PORT_SEC		0x44 /* SEC */
+#define IOSF_PORT_0x45		0x45
+#define IOSF_PORT_0x46		0x46
+#define IOSF_PORT_0x47		0x47
+#define IOSF_PORT_SCORE		0x48 /* SCORE */
+#define IOSF_PORT_0x55		0x55
+#define IOSF_PORT_0x58		0x58
+#define IOSF_PORT_0x59		0x59
+#define IOSF_PORT_0x5a		0x5a
 #define IOSF_PORT_USHPHY	0x61 /* USB XHCI PHY */
+#define IOSF_PORT_SCC		0x63 /* Storage Control Cluster */
 #define IOSF_PORT_LPSS		0xa0 /* LPSS - Low Power Subsystem */
+#define IOSF_PORT_0xa2		0xa2
+#define IOSF_PORT_SATAPHY	0xa3 /* SATA PHY */
+#define IOSF_PORT_PCIEPHY	0xa3 /* PCIE PHY */
+#define IOSF_PORT_SSUS		0xa8 /* SUS */
+#define IOSF_PORT_CCU		0xa9 /* Clock control unit. */
 
 /* Read and write opcodes differ per port. */
+#define IOSF_OP_READ_AUNIT	0x10
+#define IOSF_OP_WRITE_AUNIT	(IOSF_OP_READ_AUNIT | 1)
 #define IOSF_OP_READ_SYSMEMC	0x10
 #define IOSF_OP_WRITE_SYSMEMC	(IOSF_OP_READ_SYSMEMC | 1)
+#define IOSF_OP_READ_CPU_BUS	0x10
+#define IOSF_OP_WRITE_CPU_BUS	(IOSF_OP_READ_CPU_BUS | 1)
 #define IOSF_OP_READ_BUNIT	0x10
 #define IOSF_OP_WRITE_BUNIT	(IOSF_OP_READ_BUNIT | 1)
+#define IOSF_OP_READ_PMC	0x06
+#define IOSF_OP_WRITE_PMC	(IOSF_OP_READ_PMC | 1)
+#define IOSF_OP_READ_GFX	0x00
+#define IOSF_OP_WRITE_GFX	(IOSF_OP_READ_GFX | 1)
+#define IOSF_OP_READ_SYSMEMIO	0x06
+#define IOSF_OP_WRITE_SYSMEMIO	(IOSF_OP_READ_SYSMEMIO | 1)
+#define IOSF_OP_READ_USBPHY	0x06
+#define IOSF_OP_WRITE_USBPHY	(IOSF_OP_READ_USBPHY | 1)
+#define IOSF_OP_READ_SEC	0x04
+#define IOSF_OP_WRITE_SEC	(IOSF_OP_READ_SEC | 1)
+#define IOSF_OP_READ_0x45	0x06
+#define IOSF_OP_WRITE_0x45	(IOSF_OP_READ_0x45 | 1)
+#define IOSF_OP_READ_0x46	0x06
+#define IOSF_OP_WRITE_0x46	(IOSF_OP_READ_0x46 | 1)
+#define IOSF_OP_READ_0x47	0x06
+#define IOSF_OP_WRITE_0x47	(IOSF_OP_READ_0x47 | 1)
+#define IOSF_OP_READ_SCORE	0x06
+#define IOSF_OP_WRITE_SCORE	(IOSF_OP_READ_SCORE | 1)
+#define IOSF_OP_READ_0x55	0x04
+#define IOSF_OP_WRITE_0x55	(IOSF_OP_READ_0x55 | 1)
+#define IOSF_OP_READ_0x58	0x06
+#define IOSF_OP_WRITE_0x58	(IOSF_OP_READ_0x58 | 1)
+#define IOSF_OP_READ_0x59	0x06
+#define IOSF_OP_WRITE_0x59	(IOSF_OP_READ_0x59 | 1)
+#define IOSF_OP_READ_0x5a	0x04
+#define IOSF_OP_WRITE_0x5a	(IOSF_OP_READ_0x5a | 1)
+#define IOSF_OP_READ_USHPHY	0x06
+#define IOSF_OP_WRITE_USHPHY	(IOSF_OP_READ_USHPHY | 1)
+#define IOSF_OP_READ_SCC	0x06
+#define IOSF_OP_WRITE_SCC	(IOSF_OP_READ_SCC | 1)
 #define IOSF_OP_READ_LPSS	0x06
 #define IOSF_OP_WRITE_LPSS	(IOSF_OP_READ_LPSS | 1)
+#define IOSF_OP_READ_0xa2	0x06
+#define IOSF_OP_WRITE_0xa2	(IOSF_OP_READ_0xa2 | 1)
+#define IOSF_OP_READ_SATAPHY	0x00
+#define IOSF_OP_WRITE_SATAPHY	(IOSF_OP_READ_SATAPHY | 1)
+#define IOSF_OP_READ_PCIEPHY	0x00
+#define IOSF_OP_WRITE_PCIEPHY	(IOSF_OP_READ_PCIEPHY | 1)
+#define IOSF_OP_READ_SSUS	0x10
+#define IOSF_OP_WRITE_SSUS	(IOSF_OP_READ_SSUS | 1)
+#define IOSF_OP_READ_CCU	0x06
+#define IOSF_OP_WRITE_CCU	(IOSF_OP_READ_CCU | 1)
 
 /*
  * BUNIT Registers.
@@ -94,10 +194,18 @@ void iosf_lpss_write(int reg, uint32_t val);
 #define BUNIT_BMBOUND_HI	0x26
 #define BUNIT_MMCONF_REG	0x27
 /* The SMMRR registers define the SMM region in MiB granularity. */
+#define BUNIT_SMRCP		0x2b
+#define BUNIT_SMRRAC		0x2c
+#define BUNIT_SMRWAC		0x2d
 #define BUNIT_SMRRL		0x2e
 #define BUNIT_SMRRH		0x2f
 # define BUNIT_SMRR_ENABLE	(1 << 31)
 
+/* SA ID bits. */
+#define SAI_IA_UNTRUSTED	(1 << 0)
+#define SAI_IA_SMM		(1 << 2)
+#define SAI_IA_BOOT		(1 << 4)
+
 /*
  * DUNIT Registers.
  */
@@ -116,6 +224,46 @@ void iosf_lpss_write(int reg, uint32_t val);
 # define DTR0_SPEED_1333	0x02
 # define DTR0_SPEED_1600	0x03
 
+/*
+ * PUNIT Registers
+ */
+#define SB_BIOS_CONFIG			0x06
+# define  SB_BIOS_CONFIG_ECC_EN			(1 << 31)
+# define  SB_BIOS_CONFIG_DUAL_CH_DIS		(1 << 30)
+# define  SB_BIOS_CONFIG_EFF_ECC		(1 << 29)
+# define  SB_BIOS_CONFIG_EFF_DUAL_CH_DIS	(1 << 28)
+# define  SB_BIOS_CONFIG_PERF_MODE		(1 << 17)
+# define  SB_BIOS_CONFIG_PDM_MODE		(1 << 16)
+# define  SB_BIOS_CONFIG_DDRIO_PWRGATE		(1 << 8)
+# define  SB_BIOS_CONFIG_GFX_TURBO_DIS		(1 << 7)
+# define  SB_BIOS_CONFIG_PS2_EN_VNN		(1 << 3)
+# define  SB_BIOS_CONFIG_PS2_EN_VCC		(1 << 2)
+# define  SB_BIOS_CONFIG_PCIE_PLLOFFOK		(1 << 1)
+# define  SB_BIOS_CONFIG_USB_CACHING_EN		(1 << 0)
+#define BIOS_RESET_CPL			0x05
+# define  BIOS_RESET_CPL_ALL_DONE		(1 << 1)
+# define  BIOS_RESET_CPL_RESET_DONE		(1 << 0)
+#define PUNIT_PWRGT_CONTROL		0x60
+#define PUNIT_PWRGT_STATUS		0x61
+#define PUNIT_GPU_EC_VIRUS		0xd2
+
+#define PUNIT_SOC_POWER_BUDGET		0x02
+#define PUNIT_SOC_ENERGY_CREDIT		0x03
+#define PUNIT_PTMC			0x80
+#define PUNIT_GFXT			0x88
+#define PUNIT_VEDT			0x89
+#define PUNIT_ISPT			0x8c
+#define PUNIT_PTPS			0xb2
+#define PUNIT_TE_AUX0			0xb5
+#define PUNIT_TE_AUX1			0xb6
+#define PUNIT_TE_AUX2			0xb7
+#define PUNIT_TE_AUX3			0xb8
+#define PUNIT_TTE_VRIccMax		0xb9
+#define PUNIT_TTE_VRHot			0xba
+#define PUNIT_TTE_XXPROCHOT		0xbb
+#define PUNIT_TTE_SLM0			0xbc
+#define PUNIT_TTE_SLM1			0xbd
+#define PUNIT_TTE_SWT			0xbf
 
 /*
  * LPSS Registers
@@ -188,4 +336,11 @@ void iosf_lpss_write(int reg, uint32_t val);
 #define USHPHY_REE_DAC_CONTROL			0x80b8
 #define USHPHY_CDN_U1_POWER_STATE_DEF		0x0000
 
+/*
+ * LPE Registers
+ */
+#define LPE_PCICFGCTR1			0x0500
+# define LPE_PCICFGCTR1_PCI_CFG_DIS		(1 << 0)
+# define LPE_PCICFGCTR1_ACPI_INT_EN		(1 << 1)
+
 #endif /* _BAYTRAIL_IOSF_H_ */
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index e6b6039ad1..35000254b4 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google, Inc.
  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2016 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -93,6 +94,36 @@ void iosf_dunit_write(int reg, uint32_t val)
 	iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val);
 }
 
+uint32_t iosf_punit_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(PMC), reg);
+}
+
+void iosf_punit_write(int reg, uint32_t val)
+{
+	iosf_write_port(IOSF_WRITE(PMC), reg, val);
+}
+
+uint32_t iosf_usbphy_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(USBPHY), reg);
+}
+
+void iosf_usbphy_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(USBPHY), reg, val);
+}
+
+uint32_t iosf_ushphy_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(USHPHY), reg);
+}
+
+void iosf_ushphy_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(USHPHY), reg, val);
+}
+
 uint32_t iosf_lpss_read(int reg)
 {
 	return iosf_read_port(IOSF_READ(LPSS), reg);
@@ -102,3 +133,153 @@ void iosf_lpss_write(int reg, uint32_t val)
 {
 	return iosf_write_port(IOSF_WRITE(LPSS), reg, val);
 }
+
+uint32_t iosf_ccu_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(CCU), reg);
+}
+
+void iosf_ccu_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(CCU), reg, val);
+}
+
+uint32_t iosf_score_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(SCORE), reg);
+}
+
+void iosf_score_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(SCORE), reg, val);
+}
+
+uint32_t iosf_scc_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(SCC), reg);
+}
+
+void iosf_scc_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(SCC), reg, val);
+}
+
+uint32_t iosf_aunit_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(AUNIT), reg);
+}
+
+void iosf_aunit_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(AUNIT), reg, val);
+}
+
+uint32_t iosf_cpu_bus_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(CPU_BUS), reg);
+}
+
+void iosf_cpu_bus_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val);
+}
+
+uint32_t iosf_sec_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(SEC), reg);
+}
+
+void iosf_sec_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(SEC), reg, val);
+}
+
+uint32_t iosf_port45_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x45), reg);
+}
+
+void iosf_port45_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x45), reg, val);
+}
+
+uint32_t iosf_port46_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x46), reg);
+}
+
+void iosf_port46_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x46), reg, val);
+}
+
+uint32_t iosf_port47_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x47), reg);
+}
+
+void iosf_port47_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x47), reg, val);
+}
+
+uint32_t iosf_port55_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x55), reg);
+}
+
+void iosf_port55_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x55), reg, val);
+}
+
+uint32_t iosf_port58_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x58), reg);
+}
+
+void iosf_port58_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x58), reg, val);
+}
+
+uint32_t iosf_port59_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x59), reg);
+}
+
+void iosf_port59_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x59), reg, val);
+}
+
+uint32_t iosf_port5a_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0x5a), reg);
+}
+
+void iosf_port5a_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0x5a), reg, val);
+}
+
+uint32_t iosf_porta2_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(0xa2), reg);
+}
+
+void iosf_porta2_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(0xa2), reg, val);
+}
+
+uint32_t iosf_ssus_read(int reg)
+{
+	return iosf_read_port(IOSF_READ(SSUS), reg);
+}
+
+void iosf_ssus_write(int reg, uint32_t val)
+{
+	return iosf_write_port(IOSF_WRITE(SSUS), reg, val);
+}
-- 
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