From 9c1a335fbcbadb01a89c1dc59dae6094e0d13bc0 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 6 Jan 2021 20:52:16 -0800 Subject: mb/google/volteer: Configure Delbin USB2 ports for Type C Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202 Reviewed-by: Tim Wawrzynczak Reviewed-by: Chiranjeevi Rapolu Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/delbin/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 577404737b..aa06d09e8a 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,7 +51,9 @@ chip soc/intel/tigerlake .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_56P3MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Acoustic settings register "AcousticNoiseMitigation" = "1" -- cgit v1.2.3