From 9b6a3a0370ef310c36d5457e8cb0bb752a8418e8 Mon Sep 17 00:00:00 2001
From: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Date: Thu, 15 Jul 2021 11:39:01 +0800
Subject: mb/google/dedede/var/pirika: Add USB2 PHY parameters

This change adds fine-tuned USB2 PHY parameters for pirika.

BUG=192601233
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/google/dedede/variants/pirika/overridetree.cb | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
index b7fef8b6e3..df3fead3d9 100644
--- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb
@@ -37,7 +37,19 @@ chip soc/intel/jasperlake
 	}"
 
 	# USB Port Configuration
+	register "usb2_ports[2]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}"	# Type-A
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
+	register "usb2_ports[7]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.pre_emp_bias  = USB2_BIAS_11P25MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" 	# Integrated Bluetooth
 
 	register "tcc_offset" = "8"     # TCC of 97C
 
-- 
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