From 99dcf231f48433a07cbd47ecb0c23301a6b5b34e Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 30 Sep 2003 02:16:47 +0000 Subject: The epia now works. Now to fix the ram ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/devices/device.c | 22 ++++++---- src/devices/pci_device.c | 4 ++ src/devices/root_device.c | 6 +++ src/mainboard/via/epia/Config.lb | 20 ++++----- src/mainboard/via/epia/mainboard.c | 11 ++++- src/northbridge/via/vt8601/northbridge.c | 72 +++++--------------------------- src/northbridge/via/vt8601/raminit.c | 2 +- src/southbridge/via/vt8231/vt8231.c | 8 ++++ targets/via/epia/Config.lb | 8 ++-- 9 files changed, 69 insertions(+), 84 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index e52cc2a57e..289c0766ea 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -251,6 +251,17 @@ void compute_allocate_resource( min_align = 0; base = bridge->base; + printk_spew("%s: bus %p, bridge %p, type_mask 0x%x, type 0x%x\n", + __FUNCTION__, + bus, bridge, type_mask, type); + printk_spew("vendor 0x%x device 0x%x class 0x%x \n", + bus->dev->vendor, bus->dev->device, bus->dev->class); + printk_spew("%s compute_allocate_%s: base: %08lx size: %08lx align: %d gran: %d\n", + dev_path(bus->dev), + (bridge->flags & IORESOURCE_IO)? "io": + (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran); + /* We want different minimum alignments for different kinds of * resources. These minimums are not device type specific * but resource type specific. @@ -262,12 +273,6 @@ void compute_allocate_resource( min_align = log2(DEVICE_MEM_ALIGN); } - printk_spew("%s compute_allocate_%s: base: %08lx size: %08lx align: %d gran: %d\n", - dev_path(dev), - (bridge->flags & IORESOURCE_IO)? "io": - (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran); - /* Make certain I have read in all of the resources */ read_resources(bus); @@ -439,12 +444,13 @@ void dev_enumerate(void) void dev_configure(void) { struct device *root = &dev_root; - printk_info("Allocating resources..."); + printk_info("%s: Allocating resources...", __FUNCTION__); printk_debug("\n"); root->ops->read_resources(root); + printk_spew("%s: done reading resources...\n", __FUNCTION__); /* Make certain the io devices are allocated somewhere * safe. */ @@ -459,8 +465,10 @@ void dev_configure(void) root->resource[1].flags |= IORESOURCE_SET; // now just set things into registers ... we hope ... root->ops->set_resources(root); + printk_spew("%s: done setting resources...\n", __FUNCTION__); allocate_vga_resource(); + printk_spew("%s: done vga resources...\n", __FUNCTION__); printk_info("done.\n"); } diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index c387f3569f..a4789d22f4 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -174,6 +174,7 @@ static void pci_bridge_read_bases(struct device *dev) /* FIXME handle bridges without some of the optional resources */ + printk_spew("%s: path %s\n", __FUNCTION__, dev_path(dev)); /* Initialize the io space constraints on the current bus */ dev->resource[reg].base = 0; dev->resource[reg].size = 0; @@ -213,6 +214,7 @@ static void pci_bridge_read_bases(struct device *dev) reg++; dev->resources = reg; + printk_spew("DONE %s: path %s\n", __FUNCTION__, dev_path(dev)); } @@ -630,6 +632,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) uint32_t buses; uint16_t cr; + printk_spew("%s: dev %p, max %d\n", __FUNCTION__, dev, max); bus = &dev->link[0]; dev->links = 1; @@ -673,5 +676,6 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) pci_write_config32(dev, PCI_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); + printk_spew("%s returns max %d\n", __FUNCTION__, max); return max; } diff --git a/src/devices/root_device.c b/src/devices/root_device.c index c05a2cd015..ae02277363 100644 --- a/src/devices/root_device.c +++ b/src/devices/root_device.c @@ -11,6 +11,7 @@ void root_dev_read_resources(device_t root) { int res = 0; + printk_spew("%s . Root is %p\n", __FUNCTION__, root); /* Initialize the system wide io space constraints */ root->resource[res].base = 0x400; root->resource[res].size = 0; @@ -19,6 +20,8 @@ void root_dev_read_resources(device_t root) root->resource[res].limit = 0xffffUL; root->resource[res].flags = IORESOURCE_IO; root->resource[res].index = 0; + printk_spew("%s . link %p, resource %p\n", __FUNCTION__, + &root->link[0], &root->resource[res]); compute_allocate_resource(&root->link[0], &root->resource[res], IORESOURCE_IO, IORESOURCE_IO); res++; @@ -31,11 +34,14 @@ void root_dev_read_resources(device_t root) root->resource[res].limit = 0xffffffffUL; root->resource[res].flags = IORESOURCE_MEM; root->resource[res].index = 1; + printk_spew("%s . link %p, resource %p\n", __FUNCTION__, + &root->link[0], &root->resource[res]); compute_allocate_resource(&root->link[0], &root->resource[res], IORESOURCE_MEM, IORESOURCE_MEM); res++; root->resources = res; + printk_spew("%s DONE\n", __FUNCTION__); } /** diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index c4527cec17..c32c4decb0 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -208,22 +208,22 @@ dir /pc80 config chip.h northbridge via/vt8601 "vt8601" - pci 0:18.0 - pci 0:18.0 - pci 0:18.0 - pci 0:18.1 - pci 0:18.2 - pci 0:18.3 +# pci 0:0.0 +# pci 0:1.0 southbridge via/vt8231 "vt8231" +# pci 0:11.0 +# pci 0:11.1 +# pci 0:11.2 +# pci 0:11.3 +# pci 0:11.4 +# pci 0:11.5 +# pci 0:11.6 +# pci 0:12.0 register "enable_usb" = "0" register "enable_native_ide" = "1" register "enable_com_ports" = "1" register "enable_keyboard" = "0" register "enable_nvram" = "1" - pci 0:0.0 - pci 0:0.1 - pci 0:1.0 - pci 0:1.1 end end diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c index 554c0d3336..df52081ac7 100644 --- a/src/mainboard/via/epia/mainboard.c +++ b/src/mainboard/via/epia/mainboard.c @@ -9,13 +9,22 @@ #include #include "chip.h" +static int +mainboard_scan_bus(device_t root, int maxbus) +{ + int retval; + printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus); + retval = pci_scan_bus(root->bus, 0, 0xff, maxbus); + printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus); + return maxbus; +} static struct device_operations mainboard_operations = { .read_resources = root_dev_read_resources, .set_resources = root_dev_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_scan_bridge, + .scan_bus = mainboard_scan_bus, .enable = 0, }; diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 33dc4ec758..8f5d1730a6 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -20,77 +20,27 @@ struct mem_range *sizeram(void) device_t dev; int i, idx; -#warning "FIXME handle interleaved nodes" - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + dev = dev_find_slot(0, 0); if (!dev) { - printk_err("Cannot find PCI: 0:18.1\n"); + printk_err("Cannot find PCI: 0:0\n"); return 0; } - mmio_basek = (dev_root.resource[1].base >> 10); - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - -#if 1 -#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" - /* Round the mmio hold to 256M */ - mmio_basek &= ~((256*1024) - 1); -#endif + mem[0].basek = 0; + mem[0].sizek = 65536; + idx = 1; + while(idx < sizeof(mem)/sizeof(mem[0])) { + mem[idx].basek = 0; + mem[idx].sizek = 0; + idx++; + } #if 1 - printk_debug("mmio_base: %dKB\n", mmio_basek); -#endif - - for(idx = i = 0; i < 8; i++) { - uint32_t base, limit; - unsigned basek, limitk, sizek; - base = pci_read_config32(dev, 0x40 + (i<<3)); - limit = pci_read_config32(dev, 0x44 + (i<<3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - basek = (base & 0xffff0000) >> 2; - limitk = ((limit + 0x00010000) & 0xffff0000) >> 2; - sizek = limitk - basek; - if ((idx > 0) && - ((mem[idx -1].basek + mem[idx - 1].sizek) == basek)) { - mem[idx -1].sizek += sizek; - } - else { - mem[idx].basek = basek; - mem[idx].sizek = sizek; - idx++; - } - /* See if I need to split the region to accomodate pci memory space */ - if ((mem[idx - 1].basek <= mmio_basek) && - ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) { - if (mem[idx - 1].basek < mmio_basek) { - unsigned pre_sizek; - pre_sizek = mmio_basek - mem[idx - 1].basek; - mem[idx].basek = mmio_basek; - mem[idx].sizek = mem[idx - 1].sizek - pre_sizek; - mem[idx - 1].sizek = pre_sizek; - idx++; - } - if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) { - idx -= 1; - } - else { - mem[idx - 1].basek = 4*1024*1024; - mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek); - } - } - } -#if 0 for(i = 0; i < idx; i++) { printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n", i, mem[i].basek, i, mem[i].sizek); } #endif - while(idx < sizeof(mem)/sizeof(mem[0])) { - mem[idx].basek = 0; - mem[idx].sizek = 0; - idx++; - } + return mem; } static void enumerate(struct chip *chip) diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c index 7eba1cd51d..6f85189a60 100644 --- a/src/northbridge/via/vt8601/raminit.c +++ b/src/northbridge/via/vt8601/raminit.c @@ -371,7 +371,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { 0x0000, 0x8088, 0xe0ee, 0xffff // end mark }; - static cont uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, + static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57}; device_t north = 0; diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index f395b054fb..3e6372c64f 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -362,7 +362,15 @@ southbridge_init(struct chip *chip, enum chip_pass pass) } } +static void enumerate(struct chip *chip) +{ + extern struct device_operations default_pci_ops_bus; + chip_enumerate(chip); + chip->dev->ops = &default_pci_ops_bus; +} + struct chip_control southbridge_via_vt8231_control = { + .enumerate = enumerate, enable: southbridge_init, name: "VIA vt8231" }; diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb index f9d0ca5dcf..3c7524d250 100644 --- a/targets/via/epia/Config.lb +++ b/targets/via/epia/Config.lb @@ -52,8 +52,8 @@ uses LINUXBIOS_EXTRA_VERSION option CONFIG_CHIP_CONFIGURE=1 option CONFIG_KEYBOARD=1 -option MAXIMUM_CONSOLE_LOGLEVEL=8 -option DEFAULT_CONSOLE_LOGLEVEL=8 +option MAXIMUM_CONSOLE_LOGLEVEL=10 +option DEFAULT_CONSOLE_LOGLEVEL=10 option CONFIG_CONSOLE_SERIAL8250=1 option CPU_FIXUP=1 @@ -92,7 +92,7 @@ romimage "normal" option LINUXBIOS_EXTRA_VERSION=".0Normal" mainboard via/epia # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf - payload /etc/hosts + payload ../../../../tg3--ide_disk.zelf end romimage "fallback" @@ -101,7 +101,7 @@ romimage "fallback" option LINUXBIOS_EXTRA_VERSION=".0Fallback" mainboard via/epia # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf - payload /etc/hosts + payload ../../../../tg3--ide_disk.zelf end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -- cgit v1.2.3