From 9647094672eb2ea31c6192de92028614164b9d9c Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 7 Sep 2015 03:06:31 -0700 Subject: intel/sandybridge: Do not guard native VGA init by #ifdefs We don't build-test with native VGA init, so if the code is broken by a commit, we won't see it when it's guarded by #ifdefs. This has already happened in the past. Instead of gurading entire files, use the IS_ENABLED() macro, and return early. This at least enables us to build-test the code to some extent, while linker garbage collection will removed unused parts. BONUS: Indenting some blocks also makes the difference between framebuffer init and textmode init clearer. Change-Id: I334cdee214872f967ae090170d61a0e4951c6b35 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/11586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/sandybridge/gma.c | 38 +++---- .../intel/sandybridge/gma_ivybridge_lvds.c | 119 +++++++++++---------- .../intel/sandybridge/gma_sandybridge_lvds.c | 119 +++++++++++---------- 3 files changed, 140 insertions(+), 136 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index c465694383..d1779db8da 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -577,29 +577,29 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); -#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); -#endif + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); /* Post VBIOS init */ gma_pm_init_post_vbios(dev); -#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* This should probably run before post VBIOS init. */ - printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u8 *mmiobase; - u32 iobase, physbase, graphics_base; - struct northbridge_intel_sandybridge_config *conf = dev->chip_info; - iobase = dev->resource_list[2].base; - mmiobase = res2mmio(&dev->resource_list[0], 0, 0); - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - - int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); - if (lightup_ok) - gfx_set_init_done(1); -#endif + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u8 *mmiobase; + u32 iobase, physbase, graphics_base; + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; + iobase = dev->resource_list[2].base; + mmiobase = res2mmio(&dev->resource_list[0], 0, 0); + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; + + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, + mmiobase, graphics_base); + if (lightup_ok) + gfx_set_init_done(1); + } } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 65719d115e..101a3c11d3 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -34,8 +34,6 @@ #include #include -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void link_train(u8 *mmio) { write32(mmio+0xf000c,0x40); @@ -166,6 +164,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u8 edid_data[128]; struct edid edid; + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return 0; + write32(mmio + 0x00070080, 0x00000000); write32(mmio + DSPCNTR(0), 0x00000000); write32(mmio + 0x00071180, 0x00000000); @@ -238,31 +239,31 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 pixel_m2 = 1; vga_textmode_init(); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } /* Find suitable divisors. */ for (candp1 = 1; candp1 <= 8; candp1++) { @@ -408,17 +409,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + 0xf0008, 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PF_WIN_POS(0), 0); -#else - write32(mmio + PIPESRC(0), (719 << 16) | 399); - write32(mmio + PF_WIN_POS(0), 0); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PF_WIN_POS(0), 0); + } else { + write32(mmio + PIPESRC(0), (719 << 16) | 399); + write32(mmio + PF_WIN_POS(0), 0); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + } mdelay(1); @@ -428,21 +429,23 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PIPE_LINK_N1(0), link_n1); link_train(mmio); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); -#else - write32(mmio+CPU_VGACNTRL,0x298e); -#endif + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) + write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); + else + write32(mmio+CPU_VGACNTRL,0x298e); + write32(mmio+0x60100,0x44300); write32(mmio+0x60100,0x80044f00); mdelay(1); read32(mmio + 0x000f0014); // = 0x00000600 -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } write32(mmio + TRANS_HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -470,11 +473,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, mdelay(1); - write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - | TRANS_STATE_MASK -#endif - ); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC + | TRANS_STATE_MASK); + else + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC); + write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) @@ -508,10 +512,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset ((void *) lfb, 0, edid.x_resolution + * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } /* Doesn't change any hw behaviour but vga oprom expects it there. */ write32(mmio + 0x0004f040, 0x01000008); @@ -526,5 +531,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, return 1; } - -#endif diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 266883ec24..758a41d83f 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -33,8 +33,6 @@ #include #include -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void train_link(u8 *mmio) { /* Clear interrupts. */ @@ -145,6 +143,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 link_m1; u32 link_n1 = 0x00080000; + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return 0; + write32(mmio + 0x00070080, 0x00000000); write32(mmio + DSPCNTR(0), 0x00000000); write32(mmio + 0x00071180, 0x00000000); @@ -206,34 +207,34 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, target_frequency = info->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); -#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_textmode_init(); -#else - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#endif + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } /* Find suitable divisors. */ for (candp1 = 1; candp1 <= 8; candp1++) { @@ -368,15 +369,15 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); -#else - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + } mdelay(1); @@ -395,17 +396,17 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); -#else - write32(mmio + CPU_VGACNTRL, 0x20298e); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) + write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); + else + write32(mmio + CPU_VGACNTRL, 0x20298e); + train_link(mmio); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + } write32(mmio + TRANS_HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -430,11 +431,12 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + 0x00060100, 0xb01c4000); write32(mmio + 0x000f000c, 0x801a2350); mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - | TRANS_STATE_MASK -#endif - ); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) + write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC + | TRANS_STATE_MASK); + else + write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC); write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE @@ -468,10 +470,11 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset ((void *) lfb, 0, edid.x_resolution + * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), @@ -479,5 +482,3 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, return 1; } - -#endif -- cgit v1.2.3