From 95332df9d3d1aae88a6007b261e3dfc59aeba9c9 Mon Sep 17 00:00:00 2001 From: Jian Tong Date: Tue, 11 Jun 2024 14:42:06 +0800 Subject: mb/google/brox/var/lotso: Update gpio setting Based on lotso EVT schematics update gpio settings. GSPI0_CS0_L -> NF7 GSPI0_MISO -> NF7 GSPI0_MISO -> NF7 GPP_F18 -> EDGE_SINGLE BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea Signed-off-by: Jian Tong Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Kun Liu --- src/mainboard/google/brox/variants/lotso/gpio.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c index bb73882fb1..230ecaf005 100644 --- a/src/mainboard/google/brox/variants/lotso/gpio.c +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -19,14 +19,14 @@ static const struct pad_config override_gpio_table[] = { /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> GSPI0_SOC_FP_CS_L */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 * NF7: GSPI0_CLK] ==> GSPI0_SOC_FP_CLK */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> GSPI0_SOC_DI_FP_DO */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> GSPI0_SOC_DO_FP_DI */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), /* GPP_E15 : SRCCLK_OE8_L ==> SOC_GPP_E15 (NC) */ PAD_NC(GPP_E15, NONE), /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX @@ -60,6 +60,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_S6, NONE, PLTRST), /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE), }; -- cgit v1.2.3