From 93f50b35a4f89e0c514d29f27674ffedca46c08a Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 2 Dec 2021 14:18:10 +0530 Subject: soc/intel/alderlake: Add support for ADL-N CPU Type Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Kangheui Won --- src/soc/intel/alderlake/cpu.c | 11 +++++++++++ src/soc/intel/alderlake/include/soc/cpu.h | 1 + 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 94658c7acb..be115274c2 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -168,6 +168,11 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DEVICE_ID_INTEL_ADL_S_ID_15, }; + const uint16_t adl_n_mch_ids[] = { + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, + }; + const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), PCI_FUNC(SA_DEVFN_ROOT)), PCI_DEVICE_ID); @@ -187,6 +192,11 @@ enum adl_cpu_type get_adl_cpu_type(void) return ADL_S; } + for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { + if (adl_n_mch_ids[i] == mchid) + return ADL_N; + } + return ADL_UNKNOWN; } @@ -195,6 +205,7 @@ uint8_t get_supported_lpm_mask(void) enum adl_cpu_type type = get_adl_cpu_type(); switch (type) { case ADL_M: /* fallthrough */ + case ADL_N: case ADL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 233e0c2bd2..cd6f34f663 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -22,6 +22,7 @@ enum adl_cpu_type { ADL_UNKNOWN, ADL_M, + ADL_N, ADL_P, ADL_S, }; -- cgit v1.2.3