From 93f34e1a741044b13d1a666ff6ab0db2b85f74a5 Mon Sep 17 00:00:00 2001
From: Vaibhav Shankar <vaibhav.shankar@intel.com>
Date: Mon, 15 Aug 2016 11:32:26 -0700
Subject: soc/intel/apollolake: Add ASL methods for eMMC

Implement PS0 and PS3 methods to support eMMC power gate
in S0ix suspend and resume.

BUG=chrome-os-partner:53876
TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
System should resume from S0ix.

Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16233
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/apollolake/acpi/scs.asl         | 67 +++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |  3 ++
 2 files changed, 70 insertions(+)
 create mode 100644 src/soc/intel/apollolake/acpi/scs.asl

diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
new file mode 100644
index 0000000000..4108017fe6
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0) {
+	/* 0xD6- is the port address */
+	/* 0x600- is the dynamic clock gating control register offset (GENR) */
+	OperationRegion (SBMM, SystemMemory,
+				Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
+					ShiftLeft(0xD6, 16)), 0x0600), 0x18)
+	Field (SBMM, DWordAcc, NoLock, Preserve)
+	{
+		GENR, 32,
+	}
+
+	/* SCC power gate control method, this method must be serialized as
+	 * multiple device will control the GENR register
+	 *
+	 * Arguments: (2)
+	 * Arg0: 0-AND  1-OR
+	 * Arg1: Value
+	 */
+	Method (SCPG, 2, Serialized)
+	{
+		if (LEqual(Arg0, 0x1)) {
+			Or (^GENR, Arg1, ^GENR)
+		} ElseIf (LEqual(Arg0, 0x0)){
+			And (^GENR, Arg1, ^GENR)
+		}
+	}
+
+	/* eMMC */
+	Device (SDHA) {
+		Name (_ADR, 0x001C0000)
+		Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+
+		Method (_PS0, 0, NotSerialized)
+		{
+			/* Clear clock gate
+			 * Clear bit 6 and 0
+			 */
+			^^SCPG(0,0xFFFFFFBE)
+			/* Sleep 2 ms */
+			Sleep (2)
+		}
+
+		Method (_PS3, 0, NotSerialized)
+		{
+			/* Enable power gate
+			 * Restore clock gate
+			 * Restore bit 6 and 0
+			 */
+			^^SCPG(1,0x00000041)
+		}
+	} /* Device (SDHA) */
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 5b29abb557..391a531e4f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,5 +31,8 @@
 /* LPC */
 #include "lpc.asl"
 
+/* eMMC */
+#include "scs.asl"
+
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
-- 
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