From 93d5f40be51fc118a3b303f1fa515950f883f958 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Thu, 8 Jun 2017 11:00:23 -0500
Subject: soc/intel/skylake: Cache the MMIO BIOS region

If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.

Depthcharge payload loading was sped up by 75ms using this.

Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/skylake/cpu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index dddc1c3c7e..d1ed146c1b 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -34,6 +34,7 @@
 #include <cpu/x86/name.h>
 #include <cpu/x86/smm.h>
 #include <delay.h>
+#include <intelblocks/fast_spi.h>
 #include <pc80/mc146818rtc.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
@@ -569,6 +570,12 @@ static void soc_post_cpus_init(void *unused)
 {
 	if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
 		printk(BIOS_ERR, "MTRR programming failure\n");
+
+	/* Temporarily cache the memory-mapped boot media. */
+	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
+		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+		fast_spi_cache_bios_region();
+
 	x86_mtrr_check();
 }
 
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