From 9034689ee7b8e73cb524006de9538e7daf077c49 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Wed, 29 Sep 2021 21:12:27 +0200 Subject: soc/intel: deduplicate acpi_fill_soc_wake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/acpi.c | 15 --------------- src/soc/intel/apollolake/acpi.c | 15 --------------- src/soc/intel/cannonlake/acpi.c | 15 --------------- src/soc/intel/common/block/acpi/acpi.c | 1 + src/soc/intel/elkhartlake/acpi.c | 15 --------------- src/soc/intel/icelake/acpi.c | 15 --------------- src/soc/intel/jasperlake/acpi.c | 15 --------------- src/soc/intel/tigerlake/acpi.c | 15 --------------- 8 files changed, 1 insertion(+), 105 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index b28ec12483..9f4fa880a0 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -280,21 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index b6d61b19d7..8f5dd12459 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -95,21 +95,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_LOW; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 70951205e1..d0f38747cb 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -185,21 +185,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c21a861390..9bfb91ad3f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -218,6 +218,7 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint * powerbtn or any other wake source like lidopen, key board press etc. */ pm1_en = ps->pm1_en; + pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; pm1_en = acpi_fill_soc_wake(pm1_en, ps); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index abbb1ec206..7531331d25 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -249,21 +249,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index cac2138200..fa6d038a51 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -180,21 +180,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index b4efddba0c..cc7b8ae62f 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -260,21 +260,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 1a8ccb9e93..e560f11f69 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -275,21 +275,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; -- cgit v1.2.3