From 9007118f3239a4d2c9f3246d5744e4d7fdf6002a Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Wed, 10 Apr 2019 22:39:15 -0700
Subject: mb/google/hatch: Skip UART0 config in FSP

UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=b:130325418

Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
---
 src/mainboard/google/hatch/variants/hatch/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
index 28644d14cf..b9ec1dd508 100644
--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/cannonlake
 		[PchSerialIoIndexSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexSPI1] = PchSerialIoPci,
 		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
-- 
cgit v1.2.3