From 8e0bc131c8790489507a90a39f7552e607398679 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 24 Aug 2017 11:10:50 +0300 Subject: AGESA f15: Remove f10 references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode for f15 also has f10 support, so AMD_AGESA_FAMILY_10 was never selected. Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/amd/agesa/family15/romstage.c | 2 +- src/mainboard/amd/dinar/rd890_cfg.h | 5 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 9 --- src/mainboard/supermicro/h8qgi/rd890_cfg.h | 5 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.h | 5 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/buildOpts.c | 9 --- src/mainboard/tyan/s8226/rd890_cfg.h | 5 +- src/mainboard/tyan/s8226/romstage.c | 2 +- src/northbridge/amd/agesa/family10/amdfam10.h | 97 ------------------------- src/northbridge/amd/agesa/family10/reset_test.h | 49 ------------- src/northbridge/amd/agesa/family15/amdfam10.h | 97 +++++++++++++++++++++++++ src/northbridge/amd/agesa/family15/reset_test.h | 49 +++++++++++++ src/southbridge/amd/sr5650/early_setup.c | 29 +++----- 15 files changed, 170 insertions(+), 197 deletions(-) delete mode 100644 src/northbridge/amd/agesa/family10/amdfam10.h delete mode 100644 src/northbridge/amd/agesa/family10/reset_test.h create mode 100644 src/northbridge/amd/agesa/family15/amdfam10.h create mode 100644 src/northbridge/amd/agesa/family15/reset_test.h diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c index c7101996f5..e2b58c8597 100644 --- a/src/cpu/amd/agesa/family15/romstage.c +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -24,7 +24,7 @@ #include #include -#include "northbridge/amd/agesa/family10/reset_test.h" +#include "northbridge/amd/agesa/family15/reset_test.h" #include #include diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index ac3c8182a3..794c005680 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -28,11 +28,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) -#define DEFAULT_HT_PATH {0x0, 0x3} -#endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} +#else /* FAMILY10 */ +#define DEFAULT_HT_PATH {0x0, 0x3} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index b146afe0d6..e93e83e914 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = * This file include MUST occur AFTER the user option selection settings */ -/* -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) - #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#endif -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) - #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#endif -*/ - #include "MaranelloInstall.h" diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 6607094281..0227c3f54d 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -27,11 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) -#define DEFAULT_HT_PATH {0x0, 0x3} -#endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} +#else /* FAMILY10 */ +#define DEFAULT_HT_PATH {0x0, 0x3} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 79e045156f..031d0a2902 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h index 6607094281..0227c3f54d 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.h +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h @@ -27,11 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) -#define DEFAULT_HT_PATH {0x0, 0x3} -#endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} +#else /* FAMILY10 */ +#define DEFAULT_HT_PATH {0x0, 0x3} #endif #endif diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index d4fdaf2eb0..5d8351d91e 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index e27ec163ee..7c5ea5a34a 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = * This file include MUST occur AFTER the user option selection settings */ -/* -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) - #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#endif -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) - #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#endif -*/ - #include "SanMarinoInstall.h" diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 6607094281..0227c3f54d 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -27,11 +27,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) -#define DEFAULT_HT_PATH {0x0, 0x3} -#endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} +#else /* FAMILY10 */ +#define DEFAULT_HT_PATH {0x0, 0x3} #endif #endif diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 5311a87a3b..220098dadd 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h deleted file mode 100644 index 27f78a3331..0000000000 --- a/src/northbridge/amd/agesa/family10/amdfam10.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_H -#define AMDFAM10_H - -#include - -#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define BU_CFG_MSR 0xC0011023 -#define BU_CFG2_MSR 0xC001102A - -#define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 - -/* Definitions of various FAM10 registers */ -/* Function 0 */ -#define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) -#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) -#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) -#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 -#define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 - -/* Function 1 */ - -/* Function 2 */ - -/* Function 3 */ - - -/* Function 5 for FBDIMM */ -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) - -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - #if CONFIG_MAX_PHYSICAL_CPUS > 32 - #define NODE_NUMS 64 - #else - #define NODE_NUMS 32 - #endif -#else - #define NODE_NUMS 8 -#endif - -#ifdef __PRE_RAM__ -#if NODE_NUMS == 64 - #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else - #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif -#endif - -#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h deleted file mode 100644 index 61de4d9895..0000000000 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * copy from src/northbridge/amd/amdfam10/reset_test.c - */ - -#ifndef _RESET_TEST_H_ -#define _RESET_TEST_H_ - -#include -#include "amdfam10.h" /* NODE_PCI */ - -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1 << 4) -#define HTIC_BIOSR_Detect (1 << 5) -#define HTIC_INIT_Detect (1 << 6) - -static inline u32 warm_reset_detect(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -static inline void distinguish_cpu_resets(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_io_write_config32(device, HT_INIT_CONTROL, htic); -} - -#endif diff --git a/src/northbridge/amd/agesa/family15/amdfam10.h b/src/northbridge/amd/agesa/family15/amdfam10.h new file mode 100644 index 0000000000..27f78a3331 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/amdfam10.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMDFAM10_H +#define AMDFAM10_H + +#include + +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +/* Definitions of various FAM10 registers */ +/* Function 0 */ +#define HT_TRANSACTION_CONTROL 0x68 +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) +#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 +#define HTTC_DS_NP_REQ_LIMIT_MASK 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 + +/* Function 1 */ + +/* Function 2 */ + +/* Function 3 */ + + +/* Function 5 for FBDIMM */ +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + #if CONFIG_MAX_PHYSICAL_CPUS > 32 + #define NODE_NUMS 64 + #else + #define NODE_NUMS 32 + #endif +#else + #define NODE_NUMS 8 +#endif + +#ifdef __PRE_RAM__ +#if NODE_NUMS == 64 + #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif +#endif + +#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/agesa/family15/reset_test.h b/src/northbridge/amd/agesa/family15/reset_test.h new file mode 100644 index 0000000000..61de4d9895 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/reset_test.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * copy from src/northbridge/amd/amdfam10/reset_test.c + */ + +#ifndef _RESET_TEST_H_ +#define _RESET_TEST_H_ + +#include +#include "amdfam10.h" /* NODE_PCI */ + +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) + +static inline u32 warm_reset_detect(u8 nodeid) +{ + u32 htic; + pci_devfn_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); +} + +static inline void distinguish_cpu_resets(u8 nodeid) +{ + u32 htic; + pci_devfn_t device; + device = NODE_PCI(nodeid, 0); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); + htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; + pci_io_write_config32(device, HT_INIT_CONTROL, htic); +} + +#endif diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 6b4d81a62a..88ed41cb41 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -49,13 +49,15 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) } -/* family 10 only, for reg > 0xFF */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) -static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, - u32 val) +static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, + u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; + + /* family 10 only, for reg > 0xFF */ + if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)) + return; + reg = reg_old = pci_read_config32(fam10_dev, reg_pos); reg &= ~mask; reg |= val; @@ -63,10 +65,6 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m pci_write_config32(fam10_dev, reg_pos, reg); } } -#else -#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0) -#endif - /* * Compliant with CIM_33's ATINB_PrepareInit @@ -222,8 +220,7 @@ void sr5650_htinit(void) /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -269,7 +266,7 @@ void sr5650_htinit(void) //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26); /* HT Buffer Allocation for Ganged Links!!! */ -#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ } } @@ -301,8 +298,6 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void) } } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; @@ -310,6 +305,9 @@ void fam10_optimization(void) msr_t msr; u32 val; + if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)) + return; + printk(BIOS_INFO, "fam10_optimization()\n"); msr = rdmsr(0xC001001F); msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ @@ -329,9 +327,6 @@ void fam10_optimization(void) /* TODO: HT Buffer Allocation for (un)Ganged Links */ /* rpr Table 5-11, 5-12 */ } -#else -#define fam10_optimization() do {} while (0) -#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE -- cgit v1.2.3