From 8d6eae5d6d601934bc85fc07040af0dd853058b8 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 8 Jan 2020 14:25:55 -0800 Subject: mb/tglrvp: update gpio pin mux for NVMe BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 48ad36edb2..afe73c8763 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -19,7 +19,9 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* PCH M.2 SSD */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + PAD_CFG_GPO(GPP_H0, 1, PLTRST), }; /* Early pad configuration in bootblock */ -- cgit v1.2.3