From 8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 5 May 2021 19:46:09 +0530 Subject: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Marshall Dawson --- src/include/console/post_codes.h | 16 ++++++++-------- src/lib/hardwaremain.c | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9682e4db6c..9b2398c6fa 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -111,6 +111,14 @@ */ #define POST_PRE_HARDWAREMAIN 0x6e +/** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_HARDWAREMAIN 0x6f + /** * \brief Before Device Probe * @@ -195,14 +203,6 @@ */ #define POST_BS_PAYLOAD_BOOT 0x7b -/** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - /** * \brief Before calling FSP Notify before End of Firmware * diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 895a942222..cd4a57e96e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -442,7 +442,7 @@ void main(void) cbmem_initialize(); timestamp_add_now(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); + post_code(POST_ENTRY_HARDWAREMAIN); /* Handoff sleep type from romstage. */ acpi_is_wakeup_s3(); -- cgit v1.2.3