From 89186b2eb8167b56bf76d9cc03587d678b9bc661 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 26 Jun 2016 17:46:21 +0200 Subject: SPD: Add CAS latency 2 CAS latency = 2 support added for DDR2. Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/include/spd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/spd.h b/src/include/spd.h index 6424d33235..0bc7898749 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -147,6 +147,7 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_3_5 0x20 #define SPD_CAS_LATENCY_4_0 0x40 +#define SPD_CAS_LATENCY_DDR2_2 (1 << 2) #define SPD_CAS_LATENCY_DDR2_3 (1 << 3) #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5) -- cgit v1.2.3