From 87436bc4dd40c4cc09401e687e476c622f64a090 Mon Sep 17 00:00:00 2001
From: Jincheng Li <jincheng.li@intel.com>
Date: Wed, 25 Sep 2024 14:41:56 +0800
Subject: vc/intel/fsp/fsp2_0/graniterapids: Update to formal FSP header files
Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
.../intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h | 16 +-
.../graniterapids/ap/EnhancedWarningLogLib.h | 169 --
.../graniterapids/ap/FirmwareVersionInfoHob.h | 59 -
.../fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h | 21 +-
.../intel/fsp/fsp2_0/graniterapids/ap/FspEas.h | 17 -
.../fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h | 4 +-
.../fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h | 21 +-
.../fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h | 70 +
.../graniterapids/ap/FspExtSystemMemoryMapHob.h | 161 ++
.../intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h | 61 +
.../intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h | 8 +-
.../intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h | 233 ++-
.../intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h | 1835 +++++++++++++-------
.../intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h | 307 ++--
.../intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h | 26 +-
.../fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h | 260 +--
.../fsp2_0/graniterapids/ap/IioUniversalDataHob.h | 321 +---
.../fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h | 223 ++-
.../fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h | 7 +-
.../fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h | 52 +-
.../intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h | 16 +-
.../graniterapids/sp/EnhancedWarningLogLib.h | 169 --
.../graniterapids/sp/FirmwareVersionInfoHob.h | 59 -
.../fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h | 21 +-
.../intel/fsp/fsp2_0/graniterapids/sp/FspEas.h | 17 -
.../fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h | 4 +-
.../fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h | 21 +-
.../fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h | 70 +
.../graniterapids/sp/FspExtSystemMemoryMapHob.h | 161 ++
.../intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h | 61 +
.../intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h | 8 +-
.../intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h | 231 ++-
.../intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h | 1835 +++++++++++++-------
.../intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h | 307 ++--
.../intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h | 26 +-
.../fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h | 260 +--
.../fsp2_0/graniterapids/sp/IioUniversalDataHob.h | 319 +---
.../fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h | 223 ++-
.../fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h | 7 +-
.../fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h | 52 +-
40 files changed, 4471 insertions(+), 3267 deletions(-)
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtSystemMemoryMapHob.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h
delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtSystemMemoryMapHob.h
create mode 100644 src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h
index 42b5cc20d5..5f6afc2146 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,25 +26,32 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _CXL_NODE_HOB_
#define _CXL_NODE_HOB_
-#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
#ifndef MAX_CXL_HDM_RANGES
#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
#endif
#ifndef MAX_CXL_PER_SOCKET
-#define MAX_CXL_PER_SOCKET 8
+#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
#endif
#define CXL_NODE_ATTR_MEM BIT0
#define CXL_NODE_ATTR_PERSISTENT BIT1
#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
#define CXL_NODE_ATTR_ACCELERATOR BIT3
+#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
typedef UINT32 CXL_NODE_ATTR;
@@ -75,6 +82,7 @@ typedef struct {
UINT32 Size;
UINT8 Ways;
UINT8 SocketBitmap;
+ BOOLEAN AcpiSratSpMemFlag;
CXL_EFI_MEM_TYPE EfiMemType;
CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
@@ -86,7 +94,7 @@ typedef struct {
//
// CXL node info for UEFI memory map and ACPI tables construction
//
- CXL_NODE_INFO CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
+ CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
} CXL_NODE_SOCKET;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h
deleted file mode 100644
index 7c54749304..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _ENHANCED_WARNING_LOG_LIB_
-#define _ENHANCED_WARNING_LOG_LIB_
-
-#define FSP_RESERVED_LEN 12
-
-#pragma pack(1)
-
-///
-/// Enhanced Warning Log Header
-///
-typedef struct {
- EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
- UINT32 Size; /// Total size in bytes including the header and buffer
- UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
- /// of the buffer immediately following this structure
- /// Can be used to determine if buffer has sufficient space for next entry
- UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
- /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
- /// Consumers can ignore CRC check if not needed.
- UINT32 Reserved; /// Reserved for future use, must be initialized to 0
-} EWL_HEADER;
-
-///
-/// List of all entry types supported by this revision of EWL
-///
-typedef enum {
- EwlType0 = 0,
- EwlType1 = 1,
- EwlType2 = 2,
- EwlType3 = 3,
- EwlType4 = 4,
- EwlType5 = 5,
- EwlType6 = 6,
- EwlType7 = 7,
- EwlType8 = 8,
- EwlType9 = 9,
- EwlType10 = 10,
- EwlType11 = 11,
- EwlType12 = 12,
- EwlType13 = 13,
- EwlType14 = 14,
- EwlType15 = 15,
- EwlType16 = 16,
- EwlType17 = 17,
- EwlType18 = 18,
- EwlType19 = 19,
- EwlType20 = 20,
- EwlType21 = 21,
- EwlType22 = 22,
- EwlType23 = 23,
- EwlType24 = 24,
- EwlType25 = 25,
- EwlType26 = 26,
- EwlType27 = 27,
- EwlType28 = 28,
- EwlType29 = 29,
- EwlType30 = 30,
- EwlType31 = 31,
- EwlType32 = 32,
- EwlTypeMax,
- EwlTypeOem = 0x8000,
- EwlTypeDelim = MAX_INT32
-} EWL_TYPE;
-
-///
-/// EWL severities
-///
-typedef enum {
- EwlSeverityInfo,
- EwlSeverityWarning,
- EwlSeverityFatal,
- EwlSeverityMax,
- EwlSeverityDelim = MAX_INT32
-} EWL_SEVERITY;
-
-
-///
-/// Generic entry header for parsing the log
-///
-typedef struct {
- EWL_TYPE Type;
- UINT16 Size; /// Entries will be packed by byte in contiguous space
- EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
-} EWL_ENTRY_HEADER;
-
-///
-/// Legacy content provides context of the warning
-///
-typedef struct {
- UINT8 MajorCheckpoint; // EWL Spec - Appendix B
- UINT8 MinorCheckpoint;
- UINT8 MajorWarningCode; // EWL Spec - Appendix A
- UINT8 MinorWarningCode;
-} EWL_ENTRY_CONTEXT;
-
-///
-/// Legacy content to specify memory location
-///
-typedef struct {
- UINT8 Socket; /// 0xFF = n/a
- UINT8 Channel; /// 0xFF = n/a
- UINT8 PseudoChannel; /// 0xFF = n/a
- UINT8 Dimm; /// 0xFF = n/a
- UINT8 Rank; /// 0xFF = n/a
-} EWL_ENTRY_MEMORY_LOCATION;
-
-///
-/// Type 3 = Enhanced type for command, control IO errors
-///
-typedef struct {
- EWL_ENTRY_HEADER Header;
- EWL_ENTRY_CONTEXT Context;
- EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
- UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
- UINT8 EyeSize; // 0xFF = n/a
-} EWL_ENTRY_TYPE3;
-
-#pragma pack()
-
-///
-/// Enhanced Warning Log Spec defined data log structure
-///
-typedef struct {
- EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
- UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
-} EWL_PUBLIC_DATA;
-
-///
-/// EWL private data structure. This is going to be implementation dependent
-/// When we separate OEM hooks via a PPI, we can remove this
-///
-typedef struct {
- UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
- UINT32 numEntries; // Number of entries currently logged
- EWL_PUBLIC_DATA status; // Spec defined EWL
-} EWL_PRIVATE_DATA;
-
-
-#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h
deleted file mode 100644
index 5d09dd2d18..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/** @file
- Header file for Firmware Version Information
- @copyright
- Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
- UINT8 Count; ///< Offset 28 Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
index 6d5ba0a37b..7150e5ed8e 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,15 +26,28 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
-#ifndef _FSP_ACPI_HOBS_H_
-#define _FSP_ACPI_HOBS_H_
+#ifndef __FSP_ACPI_HOBS__
+#define __FSP_ACPI_HOBS__
+
+//Typecast HOB pointer to APEI table structure of ACPI version 6.2
+#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
//Typecast HOB pointer to ACPI CXL CEDT table structure
#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
+
+// Typecast HOB pointer to EWL_PRIVATE_DATA.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
+
//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
-#endif //#ifndef _FSP_ACPI_HOBS_H_
+#endif // __FSP_ACPI_HOBS__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h
deleted file mode 100644
index f99c3bc36b..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
- Intel FSP definition from Intel Firmware Support Package External
- Architecture Specification v2.2.
- @copyright
- Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _FSP_EAS_H_
-#define _FSP_EAS_H_
-
-#include <Uefi.h>
-#include <Guid/GuidHobFspEas.h>
-#include <Guid/FspHeaderFile.h>
-#include <FspEas/FspApi.h>
-
-#endif // _FSP_EAS_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
index af0dc5055e..ce694e9c91 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef __FSP_EDPC_PARAM__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h
index ecc2d6fdf7..6b418c514c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,20 +26,23 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _FSP_ERROR_INFO_HOB_H_
#define _FSP_ERROR_INFO_HOB_H_
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-#include <Pi/PiStatusCode.h>
-
-#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
+///
+/// GUID value indicating the FSP error information.
+///
+#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
+#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
+///
+/// FSP Error Information Block.
+///
#pragma pack(1)
-
typedef struct {
///
/// GUID HOB header.
@@ -81,4 +84,4 @@ typedef struct {
#pragma pack()
-#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
+#endif //_FSP_ERROR_INFO_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h
new file mode 100644
index 0000000000..97e3710965
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h
@@ -0,0 +1,70 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
+#define _FSP_EXT_MEMORY_PPR_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
+
+#pragma pack(1)
+
+typedef struct FspExtPprAddr {
+ UINT8 Status;
+ UINT8 ErrorType;
+ UINT8 Socket;
+ UINT8 MemoryController;
+ UINT8 Channel;
+ UINT8 Dimm;
+ UINT8 Bank;
+ UINT32 Row;
+ UINT8 Rank;
+} FSP_EXT_PPR_ADDR;
+
+typedef struct FspExtPprDdrInfo {
+ UINT8 Count;
+ FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
+} FSP_EXT_DDR_PPR_INFO;
+
+typedef struct FspExtMemoryPprData {
+ FSP_EXT_DDR_PPR_INFO DdrPprInfo;
+} FSP_EXT_MEMORY_PPR_DATA;
+
+typedef struct FspExtMemoryPprHob {
+ FSP_EXT_HEADER Header;
+ FSP_EXT_MEMORY_PPR_DATA Data;
+} FSP_EXT_MEMORY_PPR_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_MEMORY_PPR_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtSystemMemoryMapHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtSystemMemoryMapHob.h
new file mode 100644
index 0000000000..864d53ac45
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtSystemMemoryMapHob.h
@@ -0,0 +1,161 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
+
+#pragma pack(1)
+
+typedef struct FspDimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MCR NumRanks and NumPackageRanks may differ
+ UINT8 ActKeyByte2; // Actual module type reported by SPD
+ UINT16 DimmSize;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
+ UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ INT32 CommonTck;
+ UINT16 SpdRegVen; // Register Vendor ID in SPD
+ UINT8 DataWidth;
+} FSP_EXT_DIMM_DEVICE;
+
+typedef struct FspExtMemoryDimmDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
+} FSP_EXT_DIMM_DEVICE_INFO;
+
+typedef struct FspMemoryChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 ChFailed;
+ UINT8 NgnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
+} FSP_EXT_MEMORY_CHANNEL_DEVICE;
+
+typedef struct FspMemoryController {
+ UINT8 ImcEnabled;
+ UINT32 MemSize;
+} FSP_EXT_MEMORY_CONTROLLER;
+
+typedef struct FspExtMemoryChannelDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
+} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
+
+typedef struct FspExtMemoryControllerInfo {
+ UINT8 Count;
+ UINT8 NumChPerMC;
+ FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
+} FSP_EXT_MEMORY_CONTROLLER_INFO;
+
+typedef struct FspMemoryMapSocket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
+} FSP_EXT_MEMORY_MAP_SOCKET;
+
+typedef struct FspExtMemMapSocketInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
+} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
+
+typedef struct FspMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} FSP_EXT_MEMORY_MAP_ELEMENT;
+
+typedef struct FspExtMemMapElementInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
+} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
+
+typedef struct FspExtRasInfo {
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+} FSP_EXT_RAS_INFO;
+
+typedef struct FspExtMemoryConfigurationInfo {
+ UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT32 MemSize; // Total physical memory size
+ UINT16 MemFreq;
+ UINT8 MemMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage; // Mem Frequency
+ UINT8 ErrorCorrectionType;
+} FSP_EXT_MEMORY_CONFIGURATION_INFO;
+
+typedef struct FspExtSystemMemoryMapData {
+ FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
+ FSP_EXT_RAS_INFO RasInfo;
+ FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
+ FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
+} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
+
+typedef struct FspExtSystemMemoryMapDataHob{
+ FSP_EXT_HEADER Header;
+ FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
+} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h
new file mode 100644
index 0000000000..c8df3acaef
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h
@@ -0,0 +1,61 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_GLOBALS_
+#define _FSP_EXT_GLOBALS_
+
+#define FSP_MAX_SOCKET MAX_SOCKET
+#define FSP_MAX_IMC MAX_IMC
+#define FSP_MAX_MC_CH MAX_MC_CH
+#define FSP_MAX_DIMM MAX_DIMM
+#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
+#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
+#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
+#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
+
+typedef struct FspExtHeader {
+ UINT64 Magic;
+ UINT32 DataLength;
+ UINT32 CheckSum;
+} FSP_EXT_HEADER;
+
+#endif // _FSP_EXT_GLOBALS_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h
index d90f785578..cbee351279 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
-#define FSPT_UPD_SIGNATURE 0x545F445055525053 /* 'SPRUPD_T' */
+#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
-#define FSPM_UPD_SIGNATURE 0x4D5F445055525053 /* 'SPRUPD_M' */
+#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
-#define FSPS_UPD_SIGNATURE 0x535F445055525053 /* 'SPRUPD_S' */
+#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
index 77133a737a..ba7767267f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -35,13 +35,27 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
-#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } };
-
#pragma pack(1)
typedef struct {
- /** WHEA Support
+/** RAS Log Level.
+ RAS Log setup options.
+ 0:None, 1:MIN (BASIC_FLOW), 2:MID (BASIC_FLOW, FUNC_FLOW), 3:MAX (BASIC_FLOW, FUNC_FLOW, REG)
+**/
+ UINT8 RasLogLevel;
+
+/** WHEA FV Base Address
+ The physical memory-mapped base address of the WHEA (FV).
+**/
+ UINT64 WheaFvBase;
+
+/** WHEA FV Base Size
+ The size of the WHEA FV region in bytes
+**/
+ UINT64 WheaFvBaseSize;
+
+/** WHEA Support
Enable/Disable WHEA support.
0:Disable, 1:Enable
**/
@@ -69,15 +83,216 @@ typedef struct {
**/
UINT8 PcieErrInjActionTable;
+/** SGX Memory Error Injection Support
+ Enable/Disable Error Injection Support in SGX Memory.
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 SgxErrorInjEn;
+
+/** Os Native AER Support
+ Select FFM or OS native for AER error handling. If select OS native, BIOS also initialize
+ FFM first until handshake, which depends on OS capability in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 OsNativeAerSupport;
+
+/** IIO MCA Support.
+ Enable/Disable IIO MCA Support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 IoMcaEn;
+
+/** System Errors
+ System Error Enable/Disable setup options.
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 SystemErrorEn;
+
+/** CPU CrashLog Feature
+ The feature helps collecting crash data from OOBMSM SSRAM
+ 0:Disabled, 1:Enabled,2:Auto
+**/
+ UINT8 CpuCrashLogFeature;
+
+/** MCERR Trigger CrashLog Disable
+ The feature helps to disable MCERR to trigger crash log
+ 0:No, 1:Yes
+**/
+ UINT8 McerrTriggerDisable;
+
+/** Smbus Error Recovery
+ Enable or Disable(Default) Smbus Error Recovery
+ 0:Disabled, 1:SMI, 2:Error Pin
+**/
+ UINT8 SmbusErrorRecovery;
+
+/** EMCA Error Support
+ Enable/Disable EMCA Error support
+ 0:Disable, 1:Enable
+**/
+ UINT8 EmcaEn;
+
+/** EMCA Logging Support
+ Enable/Disable EMCA Logging
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogEn;
+
+/** LMCE Support
+ Enable/Disable Local MCE firmware support
+ 0:Disable, 1:Enable
+**/
+ UINT8 LmceEn;
+
+/** EMCA MCE-SMI Enable
+ Enable/Disable EMCA Uncorrected SMI for gen2
+ 0:Disable, 2:EMCA gen2 MSMI
+**/
+ UINT8 EmcaMsmiEn;
+
+/** EMCA CMCI-SMI Morphing
+ Enable/Disable EMCA CSMI
+ 0:Disable, 2:EMCA gen2 CSMI
+**/
+ UINT8 EmcaCsmiEn;
+
+/** EMCA CMCI-SMI Threshold
+ Set the threshold of CSMI
+**/
+ UINT16 EmcaCsmiThreshold;
+
+/** CSMI Dynamic Disable
+ Enable/Disable CSMI when error threshold reached
+ 0:Disable, 1:Enable
+**/
+ UINT8 CsmiDynamicDisable;
+
+/** Ignore OS ELOG Opt-in
+ Enable/Disable Ignore OS ELOG Opt-in and log
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogIgnOptin;
+
+/** Corrected Error eLog
+ Enable/Disable Corrected Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogCorrErrEn;
+
+/** Memory Error eLog
+ Enable/Disable Memory Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogMemErrEn;
+
+/** Processor Error eLog
+ Enable/Disable Processor Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogProcErrEn;
+
+/** Ubox Error Mask
+ Mask SMI generation for Ubox Error
+ 0:Disable, 1:Enable
+**/
+ UINT8 UboxErrorMask;
+
+/** Corrected Error Cloaking
+ Mask Corrected errors from OS/SW visibility only when EMCA is enabled
+ 0:Disable, 1:Enable
+**/
+ UINT8 CeCloakingEn;
+
+/** Memory Corrected Error
+ Enable/Disable Memory Corrected Error
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 CorrMemErrEn;
+
+/** Mca Bank Error Injection Support
+ Enable/Disable Mca Bank Error Injection Support.
+ $EN_DIS
+**/
+ UINT8 McaBankErrInjEn;
+
+/** Whea Log Memory Error
+ Enable/Disable Whea Log Memory Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogMemoryEn;
+
+/** Whea Log Processor Error
+ Enable/Disable Whea Log Processor Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogProcEn;
+
+/** Whea Log PCI Error
+ Enable/Disable Whea Log PCI Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogPciEn;
+
+/** Viral Status
+ Enable/Disable Viral
+ $EN_DIS
+**/
+ UINT8 ViralEn;
+
+/** System Memory Poison
+ Enable/Disable System Memory Poison.
+ $EN_DIS
+**/
+ UINT8 DfxPoisonEn;
+
+/** Clear Shadow Registers
+ Enable/Disable clearing shadow registers.
+ $EN_DIS
+**/
+ UINT8 ClearShadowRegisters;
+
+/** PCIE Corrected Error Threshold Counter
+ Enable/Disable PCIE Corrected Error Counter.
+ $EN_DIS
+**/
+ UINT8 PcieCorErrCntr;
+
+/** PCIE Corrected Error Threshold Counter
+ 0x00000001 - 0x0000ffff.
+**/
+ UINT32 PcieCorErrThres;
+
/** IIO eDPC Support
Enable/Disable IIO eDPC Support.
0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
**/
UINT8 EdpcEn;
+/** IIO eDPC Interrupt
+ Enable/Disable IIO eDPC Interrupt.
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 EdpcInterrupt;
+
+/** IpmiIoBase
+ Address of IpmiIoBase
+**/
+ UINT16 IpmiIoBase;
+
+/** Trigger SW Error Threshold
+ Enable or Disable Sparing trigger SW Error Match Threshold.
+ 0:Disable, 1:Enable
+**/
+ UINT8 TriggerSWErrThEn;
+
+/** SW Per Row Threshold
+ SW Per Row Correctable Error Threshold (1 - 0x7FFF) used for row level error.
+**/
+ UINT16 SparePerRowTh;
+
/** N/A
**/
- UINT8 ReservedSiliconInitUpd[16];
+ UINT8 ReservedSmmInitUpd[16];
} FSPI_CONFIG;
@@ -87,11 +302,15 @@ typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
+/** N/A
+**/
+ FSPI_ARCH_UPD FspiArchUpd;
+
/** N/A
**/
FSPI_CONFIG FspiConfig;
-
+
/** N/A
**/
UINT16 UpdTerminator;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h
index c0f09df54d..74df875686 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -30,656 +30,637 @@ are permitted provided that the following conditions are met:
**/
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
+#ifndef __FSPM_UPD_H__
+#define __FSPM_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
-
-/** FSP-M Configuration
-**/
typedef struct {
-/** Offset 0x0040 - Customer Revision
+/** Customer Revision
The Customer can set this revision string for their own purpose.
**/
UINT8 CustomerRevision[32];
-/** Offset 0x0060 - Bus Ratio
+/** Bus Ratio
Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
**/
UINT8 BusRatio[8];
-/** Offset 0x0068 - D2K Credit Config
- Set the D2K Credit Config - 1: Min, <b>2: Med(Default)</b>, 3: Max.
- 1:Min, 2:Med, 3:Max
-**/
- UINT8 D2KCreditConfig;
-
-/** Offset 0x0069 - Snoop Throttle Config
- Set the Snoop Throttle Config - <b>0: DIS(Default)</b>, 1: Min, 2: Med, 3: Max.
- 0:DIS, 1:Min, 2:Med, 3:Max
-**/
- UINT8 SnoopThrottleConfig;
-
-/** Offset 0x006A - Legacy VGA Soc
+/** Legacy VGA Soc
Socket that claims the legacy VGA range
**/
UINT8 LegacyVgaSoc;
-/** Offset 0x006B - Legacy VGA Stack
+/** Legacy VGA Stack
Stack that claims the legacy VGA range
**/
UINT8 LegacyVgaStack;
-/** Offset 0x006C - Pcie P2P Performance Mode
- Determine if to enable PCIe P2P Performance Mode - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Pcie P2P Performance Mode
+ Determine if to enable PCIe P2P Performance Mode
+ $EN_DIS
**/
UINT8 P2pRelaxedOrdering;
-/** Offset 0x006D - UPI Debug Print Level
- UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8:
- Detail, <b>0x0F: All(Default)</b>.
+/** UPI Debug Print Level
+ UPI Debug Print Level Bitmask. 0- Disable, 1- Fatal, 2- Warning, 4- Summary, 8-
+ Detail, <b>0xF- All(Default)</b>
1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
**/
UINT8 DebugPrintLevel;
-/** Offset 0x006E - NumaEn
- NumaEn - <b>1: Enable Numa(Default)</b>, 0: Disable Numa.
- 0:Disable, 1:Enable
+/** NumaEn
+ Enable or Disable Numa
+ $EN_DIS
**/
UINT8 NumaEn;
-/** Offset 0x006F - SNC
- Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, <b>0x0F: Auto(Default)</b>.
- 0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto
+/** SNC Enable
+ Enable or Disable SNC
+ 0x0:Disable, 0x1:Enable, 0x0F:Auto
**/
UINT8 SncEn;
-/** Offset 0x0070 - UMA Clustering
- Set UMA Clusters - 0: Disable, 2: Two Clusters, <b>4: Four Clusters(Default)</b>.
- 0:Disable, 2:Two Clusters, 4:Four Clusters
-**/
- UINT8 UmaClustering;
-
-/** Offset 0x0071 - IODC Mode
- IODC Mode - 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow, 4: NonAlloc,
- 5: WCILF.
+/** IODC Mode
+ IODC Mode. 0- Disable, <b>1- Auto(Default)</b>, 2- Push, 3- AllocFlow, 4- NonAlloc, 5- WCILF
0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
**/
UINT8 IoDcMode;
-/** Offset 0x0072 - Degrade Precedence
- Setup Degrade Precedence - <b>0: Topology(Default)</b>, 1: Feature.
+/** Degrade Precedence
+ Setup Degrade Precedence
0:Topology, 1:Feature
**/
UINT8 DegradePrecedence;
-/** Offset 0x0073 - Degrade 4 Socket Preference
- Setup Degrade 4 Socket Preference - <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring.
+/** Degrade 4 Socket Preference
+ Setup Degrade 4 Socket Preference
0:Fully Connect, 1:Dual Link Ring
**/
UINT8 Degrade4SPreference;
-/** Offset 0x0074 - Directory Mode
- Enable or Disable Directory Mode - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** Directory Mode
+ Enable or Disable Directory Mode
0:Disable, 1:Enable, 2:Auto
**/
UINT8 DirectoryModeEn;
-/** Offset 0x0075 - XPT Prefetch Enable
- Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** XPT Prefetch Enable
+ Enable or Disable XPT Prefetch
0:Disable, 1:Enable, 2:Auto
**/
UINT8 XptPrefetchEn;
-/** Offset 0x0076 - KTI Prefetch Enable
- Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** KTI Prefetch Enable
+ Enable or Disable KTI Prefetch
0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiPrefetchEn;
-/** Offset 0x0077 - XPT Remote Prefetch Enable
- Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** XPT Remote Prefetch Enable
+ Enable or Disable XPT Remote Prefetch Enable
0:Disable, 1:Enable, 2:Auto
**/
UINT8 XptRemotePrefetchEn;
-/** Offset 0x0078 - KTI FPGA
- Enable or Disable KTI FPGA
+/** Distress QoS Mode
+ Distress QoS. <b>0- Mode 0(Default)</b>, 2- Mode 2
+ 0:Mode 0, 2:Mode 2
**/
- UINT8 KtiFpgaEnable[8];
+ UINT8 DistressQoS;
-/** Offset 0x0080 - DDRT QoS Mode
- DDRT QoS - <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2.
- 0:Mode 0, 1:Mode 1, 2:Mode 2
-**/
- UINT8 DdrtQosMode;
-
-/** Offset 0x0081 - KTI Link Speed Mode
- Choose KTI Link Speed Mode - 0: Slow, <b>1: Full(Default)</b>.
+/** KTI Link Speed Mode
+ Choose KTI Link Speed Mode
0:Slow, 1:Full
**/
UINT8 KtiLinkSpeedMode;
-/** Offset 0x0082 - KTI Link Speed
- Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, <b>0x7F: Max KTI
- Link Speed (Default)</b>, 0x8F: Frequency Per Link.
- 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
+/** KTI Link Speed
+ Setup KTI Link Speed - 2- 160GT, 3- 200GT, 4- 240GT, <b>0x7F- Max KTI Link Speed
+ (Default)</b>, 0x8F- Frequency Per Link
+ 2:160GT, 3:200GT, 4:240GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
**/
UINT8 KtiLinkSpeed;
-/** Offset 0x0083 - KTI Link L0p
- Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Link L0p
+ Enable or Disable KTI Link L0p
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiLinkL0pEn;
-/** Offset 0x0084 - KTI Link L1
- Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Link L1
+ Enable or Disable KTI Link L1
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiLinkL1En;
-/** Offset 0x0085 - Kti Link Speed Per Port
- Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT,
- 3: 200GT, <b>0x7f: Max KTI Link Speed(Default)</b>.
- 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed
+/** Kti Link Speed Per Port
+ Setup KTI Link Speed to be allocated for each port, 2:160GT, 2:200GT, 3:240GT, 0X7f:Max
+ KTI Link Speed
**/
UINT8 KtiLinkSpeedPerPort[48];
-/** Offset 0x00B5 - DfxL0p Enable
- Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DfxL0p Enable
+ Indicates the DfxL0p Enable to be allocated for each port, 0:Disable, 1:Enable
**/
UINT8 DfxL0pEnable[48];
-/** Offset 0x00E5 - DfxL1 Enable
- Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DfxL1 Enable
+ Indicates the DfxL1 Enable to be allocated for each port, 0:Disable, 1:Enable
**/
UINT8 DfxL1Enable[48];
-/** Offset 0x0115 - KTI Failover
- Enable or Disable KTI Failover - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Failover
+ Enable or Disable KTI Failover
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiFailoverEn;
-/** Offset 0x0116 - KTI LB Enable
- Enable or Disable KTI LB - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
-**/
- UINT8 KtiLbEn;
-
-/** Offset 0x0117 - KTI CRC Mode
- Select KTI CRC Mode - <b>0: 16bit(Default)</b>, 1: 32bit, 2: Auto.
+/** KTI CRC Mode
+ Select KTI CRC Mode
0:16bit, 1:32bit, 2:Auto
**/
UINT8 KtiCrcMode;
-/** Offset 0x0118 - KTI CPU Socket Hotplug
- Enable or Disable KTI CPU Socket Hotplug - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** KTI CPU Socket Hotplug
+ Enable or Disable KTI CPU Socket Hotplug
+ $EN_DIS
**/
UINT8 KtiCpuSktHotPlugEn;
-/** Offset 0x0119 - KTI CPU Socket HotPlug Topology
- Select KTI CPU Socket HotPlug Topology - <b>0: 4Socket(Default)</b>, 1: 8Socket.
+/** KTI CPU Socket HotPlug Topology
+ Select KTI CPU Socket HotPlug Topology
0:4Socket, 1:8Socket
**/
UINT8 KtiCpuSktHotPlugTopology;
-/** Offset 0x011A - KTI SKU Mismatch Check
- Enable or Disable KTI SKU Mismatch Check - 0: Disable, <b>1 :Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** KTI SKU Mismatch Check
+ Enable or Disable KTI SKU Mismatch Check
+ $EN_DIS
**/
UINT8 KtiSkuMismatchCheck;
-/** Offset 0x011B - TOR Threshold - Loctorem threshold Normal
- Select TOR Threshold - Loctorem threshold Normal - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Low, 3: Medium, 4: High.
+/** Sdsi Contrl Ib Lock
+ Enable or Disable Sdsi Contrl Ib Lock
+ $EN_DIS
+**/
+ UINT8 SdsiCtrlIbLock;
+
+/** TOR Threshold - Loctorem threshold Normal
+ Select TOR Threshold - Loctorem threshold Normal
0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
**/
UINT8 TorThresLoctoremNorm;
-/** Offset 0x011C - TOR threshold - Loctorem threshold empty
- Select TOR threshold - Loctorem threshold empty - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Low, 3: Medium, 4:High.
+/** TOR threshold - Loctorem threshold empty
+ Select TOR threshold - Loctorem threshold empty
0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
**/
UINT8 TorThresLoctoremEmpty;
-/** Offset 0x011D - TSC Sync in Sockets
- Enable or Disable TSC Sync in Sockets - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 TscSyncEn;
-
-/** Offset 0x011E - HA A to S directory optimization
- Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, <b>2:
- Auto(Default)</b>.
+/** HA A to S directory optimization
+ Enable or Disable HA A to S directory optimization
0:Disable, 1:Enable, 2:Auto
**/
UINT8 StaleAtoSOptEn;
-/** Offset 0x011F - LLC Deadline Allocation
- Enable or Disable LLC Deadline Allocation - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
+/** LLC Deadline Allocation
+ Enable or Disable LLC Deadline Allocation
0:Disable, 1:Enable, 2:Auto
**/
UINT8 LLCDeadLineAlloc;
-/** Offset 0x0120 - MBA BW Calibration Profiles
- Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping,
- 2: Legacy BW shaping, <b>3: Auto(Default)</b>.
+/** MBA BW Calibration Profiles
+ Choice of MBA BW throttling curve
0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
**/
UINT8 MbeBWCalChoice;
-/** Offset 0x0121 - Split Lock
- Enable or Disable Split Lock - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
+/** PMM MBA BW downscale
+ PMM BW downscaling vs the baseline Total memory BW profile. Eg- picking 1/2x results
+ in scaling PMM BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:PMM BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
**/
- UINT8 SplitLock;
+ UINT8 PmmMbaBWDownscale;
-/** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket
- Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0:
- Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2:Auto
+/** CXL (Type3) MBA BW downscale
+ CXL (Type3) BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling CXL (Type3) BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:CXL BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
**/
- UINT8 M2iosfToUpiAffinity;
+ UINT8 CxlMbaBWDownscale;
-/** Offset 0x0123 - MMCFG Base Address
- Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, <b>6:
- Auto(Default)</b>.
- 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto
+/** Remote Target MBA BW downscale
+ Remote Target BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling Remote Target BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:Remote Target BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1
+ ratio, 3:8/1 ratio
**/
- UINT8 mmCfgBase;
+ UINT8 RemoteTargetMbaBWDownscale;
-/** Offset 0x0124 - MMCFG Size
- Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, <b>6: Auto(Default)</b>.
- 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto
+/** Split Lock
+ Enable or Disable Split Lock
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 mmCfgSize;
+ UINT8 SplitLock;
-/** Offset 0x0125
+/** MMCFG Base Address
+ Setup MMCFG Base Address
+ 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 0xFF:Auto
**/
- UINT8 UnusedUpdSpace0[3];
+ UINT32 mmCfgBase;
-/** Offset 0x0128 - MMIO High Base Address
- MMIO High Base Address, a hex number for Bit[51:32]
+/** MMCFG Size
+ Select MMCFG Size
+ 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 0xFF:Auto
**/
- UINT32 mmiohBase;
+ UINT32 mmCfgSize;
-/** Offset 0x012C - CPU Physical Address Limit
- CPU Physical Address Limit - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** MMIO High Base Address
+ MMIO High Base Address
+ 0:56T, 1:40T, 2:32T, 3:24T, 4:16T, 5:4T, 6:2T, 7:1T, 8:512G, 9:3584T, 10:30T, 11:60T,
+ 12:88T, 13:120T, 14:248T, 255:AUTO
**/
- UINT8 CpuPaLimit;
+ UINT32 mmiohBase;
-/** Offset 0x012D
+/** CPU Physical Address Limit
+ CPU Physical Address Limit
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace1;
+ UINT8 CpuPaLimit;
-/** Offset 0x012E - MMIO High Size
- MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
- per CPU. Range 1-1024
+/** MMIO High Size
+ MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU.
+ 0:1GB, 1:4GB, 2:16GB, 3:64GB, 4:256GB, 5:1024GB, 6:32GB, 255:AUTO
**/
- UINT16 mmiohSize;
+ UINT32 mmiohSize;
-/** Offset 0x0130 - isocEn
- Enable or Disable isocEn - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 isocEn;
-
-/** Offset 0x0131 - DCA
- Enable or Disable DCA - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** DCA
+ Enable or Disable DCA
+ $EN_DIS
**/
UINT8 dcaEn;
-/** Offset 0x0132
-**/
- UINT8 UnusedUpdSpace2[2];
-
-/** Offset 0x0134 - BoardTypeBitmask
+/** BoardTypeBitmask
BoardTypeBitmask
**/
UINT32 BoardTypeBitmask;
-/** Offset 0x0138 - AllLanesPtr
+/** S3mClkSetupPtr
+ Pointer to clk setup variable data
+**/
+ UINT64 S3mClkSetupPtr;
+
+/** AllLanesPtr
Pointer to array of ALL_LANES_EPARAM_LINK_INFO
**/
- UINT32 AllLanesPtr;
+ UINT64 AllLanesPtr;
-/** Offset 0x013C - PerLanePtr
+/** PerLanePtr
Pointer to array of PER_LANE_EPARAM_LINK_INFO
**/
- UINT32 PerLanePtr;
+ UINT64 PerLanePtr;
-/** Offset 0x0140 - AllLanesSizeOfTable
+/** AllLanesSizeOfTable
Number of elements in AllLanesPtr array.
**/
UINT32 AllLanesSizeOfTable;
-/** Offset 0x0144 - PerLaneSizeOfTable
+/** PerLaneSizeOfTable
Number of elements in PerLanePtr array.
**/
UINT32 PerLaneSizeOfTable;
-/** Offset 0x0148 - WaitTimeForPSBP
+/** WaitTimeForPSBP
Enable or Disable WaitTimeForPSBP
**/
UINT32 WaitTimeForPSBP;
-/** Offset 0x014C - WaSerializationEn
- Enable or Disable WaSerializationEn - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
-**/
- UINT8 WaSerializationEn;
-
-/** Offset 0x014D - KtiInEnableMktme
- Enable or Disable KtiInEnableMktme - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** KtiInEnableMktme
+ Enable or Disable KtiInEnableMktme
+ $EN_DIS
**/
UINT8 KtiInEnableMktme;
-/** Offset 0x014E - HIOP STACK DISABLE
+/** HIOP STACK DISABLE
Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
the bit locations are not modified. The stack order is abstracted each bit 0 =
stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
- BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32.
+ BIOS based on part-knob compatibility. The array size must be MAX_SOCKET(Maximum:8) x UINT32.
**/
- UINT8 StackDisableBitMap[32];
+ UINT32 StackDisableBitMap[8];
-/** Offset 0x016E - CFRS3mProvision
- Enable or Disable Provision S3M CFR - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Processor VmxEnable Function
+ Enable(Default) or Disable Processor VmxEnable Function
+ $EN_DIS
**/
- UINT8 CFRS3mProvision;
+ UINT8 VmxEnable;
-/** Offset 0x016F - CFRS3mManualCommit
- Enable or Disable Manual Commit S3M FW CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Smm Relocation
+ Enable(Default)/Disable Smm Relocation
+ $EN_DIS
**/
- UINT8 CFRS3mManualCommit;
+ UINT8 SmmRelocationEnable;
-/** Offset 0x0170 - CFRPucodeProvision
- Enable or Disable Provision PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Processor HyperThreading Function
+ Enables Logical processor, 0- ALL LPs, 1- Single LP, 2- Two LPs
+ 0:ALL LPs, 1:Single LP, 2:Two LPs
**/
- UINT8 CFRPucodeProvision;
+ UINT8 ProcessorLpEnable;
-/** Offset 0x0171 - CFRPucodeManualCommit
- Enable or Disable Manual Commit PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Processor Safer Mode Extensions Function
+ Enable or Disable(Default) Processor Safer Mode Extensions Function
+ $EN_DIS
**/
- UINT8 CFRPucodeManualCommit;
+ UINT8 ProcessorSmxEnable;
-/** Offset 0x0172
+/** Uncore Freq Ratio Compute
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
**/
- UINT8 UnusedUpdSpace3[2];
+ UINT8 UncoreFreqRatio;
-/** Offset 0x0174 - CFRImagePtr
- Pointer to array of CFR Image
+/** Uncore Freq Ratio IO
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
**/
- UINT32 CFRImagePtr;
+ UINT8 UncoreFreqRatioIo;
-/** Offset 0x0178 - Processor VmxEnable Function
- Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DDR frequency limit
+ Select DDR frequency limit, <b>0x00- Auto(Default)</b>, 0x01:DDR_3200, 0x03:DDR_3600,
+ 0x05:DDR_4000, 0x07:DDR_4400, 0x08:DDR_4800, 0x09:DDR_5200, 0x0A:DDR_5600, 0x0B:DDR_6000,
+ 0x0C:DDR_6400
**/
- UINT8 VmxEnable;
+ UINT8 HostDdrFreqLimit;
-/** Offset 0x0179 - Processor X2apic Function
- Enable(Default) or Disable Processor X2apic Function - 0: Disable, <b>1: Enable(Default)</b>.
+/** DDR Over Clock Enable
+ DDR Over Clock Enable, 0- Disable, 1- Enable
0:Disable, 1:Enable
**/
- UINT8 X2apic;
+ UINT8 DdrOverClockEnable;
-/** Offset 0x017A - Processor HyperThreading Function
- Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, <b>0:
- Enable(Default)</b>.
- 1:Disable, 0:Enable
+/** Advanced Debug Function
+ Select Advanced Debug Function, 0- Disable, 1- Enable, 2- Auto
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 ProcessorHyperThreadingDisable;
+ UINT8 DfxAdvDebugJumper;
-/** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function
- Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function -
- <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Memory Serial Debug Message Level
+ Select Memory Serial Debug Message Level, 0- Disable, 1- Minimum, 2- Normal, 3-
+ Maximum, <b>4- Auto(Default)</b>, 5- Fixed PCD
+ 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto, 5:Fixed PCD
**/
- UINT8 ProcessorDynamicIssEnable;
+ UINT8 serialDebugMsgLvl;
-/** Offset 0x017C - Enables Intel(R) TXT
- Enable or Disable(Default) Enables Intel(R) TXT - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** IIO IioPE0Bifurcation
+ IioPE0Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 ProcessorLtsxEnable;
+ UINT8 IioPE0Bifurcation[8];
-/** Offset 0x017D - DDR frequency limit
- Select DDR frequency limit, <b>0x00: Auto(Default)</b>, 0x13:DDR_3200, 0x16:DDR_3600,
- 0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600
+/** IIO IioPE1Bifurcation
+ IioPE1Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 DdrFreqLimit;
+ UINT8 IioPE1Bifurcation[8];
-/** Offset 0x017E - Memory Serial Debug Message Level
- Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, <b>3:
- Maximum(Default)</b>, 4: Auto.
- 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto
+/** IIO IioPE2Bifurcation
+ IioPE2Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 serialDebugMsgLvl;
+ UINT8 IioPE2Bifurcation[8];
-/** Offset 0x017F - IIO ConfigIOU0
- ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE3Bifurcation
+ IioPE3Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU0[8];
+ UINT8 IioPE3Bifurcation[8];
-/** Offset 0x0187 - IIO ConfigIOU1
- ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE4Bifurcation
+ IioPE4Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU1[8];
+ UINT8 IioPE4Bifurcation[8];
-/** Offset 0x018F - IIO ConfigIOU2
- ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE5Bifurcation
+ IioPE5Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU2[8];
+ UINT8 IioPE5Bifurcation[8];
-/** Offset 0x0197 - IIO ConfigIOU3
- ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEaBifurcation
+ IioPEaBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU3[8];
+ UINT8 IioPEaBifurcation[8];
-/** Offset 0x019F - IIO ConfigIOU4
- ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEbBifurcation
+ IioPEbBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU4[8];
+ UINT8 IioPEbBifurcation[8];
-/** Offset 0x01A7 - IIO ConfigIOU5
- ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEcBifurcation
+ IioPEcBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU5[8];
+ UINT8 IioPEcBifurcation[8];
-/** Offset 0x01AF - IIO ConfigIOU6
- ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEdBifurcation
+ IioPEdBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU6[8];
+ UINT8 IioPEdBifurcation[8];
+
+/** IIO PCIE MaxPayload Ptr
+ Pointer to array of PCIE MaxPayload settings Per Port
+**/
+ UINT32 IioPcieMaxPayloadPtr;
+
+/** IIO PCIE MaxPayload entry Number
+ Number of elements in PcieMaxPayloadPtr array, port number as unit.
+**/
+ UINT32 IioPcieMaxPayloadNumber;
+
+/** IIO Board settings Hob Ptr
+ Pointer to array of IIO_BOARD_SETTINGS_HOB
+**/
+ UINT32 IioBoardSettingsHobPtr;
+
+/** IIO Board Settings Hob length
+ The IIO Board Settings Hob Length.
+**/
+ UINT32 IioBoardSettingsHobLength;
+
+/** Iio Setup Knobs pointer
+ : Iio Setup Knobs pointer
+**/
+ UINT64 IioSetupKnobsPtr;
-/** Offset 0x01B7
+/** Iio Setup Knobs Size
+ : Iio Setup Knobs Size
**/
- UINT8 UnusedUpdSpace4;
+ UINT64 IioSetupKnobsSize;
-/** Offset 0x01B8 - IIO PCIE Config Table Ptr
- Pointer to array of UPD_IIO_PCIE_PORT_CONFIG
+/** Iio SocketConfig Setup Knobs pointer
+ : Iio SocketConfig Setup Knobs pointer
**/
- UINT32 IioPcieConfigTablePtr;
+ UINT64 IioSocketConfigSetupKnobsPtr;
-/** Offset 0x01BC - IIO PCIE Config Table Number
- Number of elements in IioPcieConfigTablePtr array, socket number as unit.
+/** Iio SocketConfig Setup Knobs Size
+ : Iio SocketConfig Setup Knobs Size
**/
- UINT32 IioPcieConfigTableNumber;
+ UINT64 IioSocketConfigSetupKnobsSize;
-/** Offset 0x01C0 - IIO DeEmphasis Array Ptr
+/** IIO DeEmphasis Array Ptr
Pointer to array of DeEmphasis
**/
UINT32 DeEmphasisPtr;
-/** Offset 0x01C4 - IIO DeEmphasis Array Number
+/** IIO DeEmphasis Array Number
Number of elements in DeEmphasis array.
**/
UINT32 DeEmphasisNumber;
-/** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr
+/** IIO PCIe Common Clock Array Ptr
Pointer to array of PCIe Common Clock
**/
UINT32 PcieCommonClockPtr;
-/** Offset 0x01CC - IIO PCIe Common Clock Array Number
+/** IIO PCIe Common Clock Array Number
Number of elements in PCIe Common Clock array.
**/
UINT32 PcieCommonClockNumber;
-/** Offset 0x01D0 - VT-d Support
- Enable or Disable VT-d Support - 0: Disable, <b>1: Enable(Default)</b>.
+/** Gen5LinkDegradation
+ Enable or disable Gen5 link degradation.
0:Disable, 1:Enable
**/
- UINT8 VtdSupport;
+ UINT8 Gen5LinkDegradation;
-/** Offset 0x01D1 - PCIe ACSCTL
- Enable/Disable overwrite of PCI Access Control Services Control register in PCI
- root ports - 0: Disable, <b>1: Enable(Default)</b>.
+/** PcieHotPlugEnable
+ Enable or disable Pcie hot plug enable feature
0:Disable, 1:Enable
**/
- UINT8 VtdPciAcsCtlWaEn;
-
-/** Offset 0x01D2
-**/
- UINT8 UnusedUpdSpace5[2];
+ UINT8 PcieHotPlugEnable;
-/** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr
- Pointer to array of Hide or visible for IIO Pcie Port.
+/** DelayAfterPCIeLinkTraining
+ Custom delay after PCI-E link training on IIO ports
**/
- UINT32 PEXPHIDEPtr;
+ UINT16 DelayAfterPCIeLinkTraining;
-/** Offset 0x01D8 - IIO PCIe Port Hide Array Number
- Number of elements in IIO PCIe Port Hide Array.
+/** MSR Lock Control
+ Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
+ remove lock bits
+ 0:Disable, 1:Enable
**/
- UINT32 PEXPHIDENumber;
+ UINT8 ProcessorMsrLockControl;
-/** Offset 0x01DC - PcieHotPlugEnable
- Enable or disable Pcie hot plug enable feature - <b>0: Disable(Default)</b>, 1: Enable.
+/** Lock Chipset
+ Lock or Unlock chipset in FSP
0:Disable, 1:Enable
**/
- UINT8 PcieHotPlugEnable;
+ UINT8 LockChipset;
-/** Offset 0x01DD
+/** DFX Ev Mode
+ When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 UnusedUpdSpace6;
+ UINT8 DfxEvMode;
-/** Offset 0x01DE - DelayAfterPCIeLinkTraining
- Custom delay after PCI-E link training on IIO ports
+/** DFX Disable Bios Done
+ When Enabled, suppresses notifying processor via MSR 151h that boot initialization
+ is finished in FSP
+ 0:Disable, 1:Enable
**/
- UINT16 DelayAfterPCIeLinkTraining;
+ UINT8 DfxDisableBiosDone;
-/** Offset 0x01E0 - IIO PCI bus resource Ptr
+/** PciBusResConfigPtr
Pointer to array of socket PCI bus resource.
**/
UINT32 PciBusResConfigPtr;
-/** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr
+/** PciBaseLimitsResConfigPtr
Pointer to array of socket PCI IO/MMIO resource.
**/
UINT32 PciBaseLimitsResConfigPtr;
-/** Offset 0x01E8 - PCH PCIE PLL Ssc
- Pointer to array of socket PCI IO/MMIO resource.
+/** PCH PCIE PLL Ssc
**/
UINT8 PchPciePllSsc;
-/** Offset 0x01E9 - MeUmaEnable
- Enable or disable ME UMA feature - <b>0: Disable(Default)</b>, 1: Enable.
+/** PchDciEn
+ Enable or <b>Disable(Default)</b> PCH DCI
0:Disable, 1:Enable
**/
- UINT8 MeUmaEnable;
+ UINT8 PchDciEn;
-/** Offset 0x01EA - SerialIoUartDebugEnable
- Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, <b>1: Enable(Default)</b>.
+/** MeUmaEnable
+ Enable or disable ME UMA feature
0:Disable, 1:Enable
**/
- UINT8 SerialIoUartDebugEnable;
+ UINT8 MeUmaEnable;
-/** Offset 0x01EB
+/** SerialIoUartDebugEnable
+ <b>Enable(Default)</b> or Disable SerialIo Uart debug library in FSP.
+ 0:Disable, 1:Enable
**/
- UINT8 UnusedUpdSpace7;
+ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x01EC - ISA Serial Base selection
- Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8,
- <b>0x3F8: 0x3F8(Default)</b>.
+/** ISA Serial Base selection
+ Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
0x2F8:0x2F8, 0x3F8:0x3F8
**/
UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x01EE - MemRefreshWaterMark
- Enable or Disable MemRefreshWaterMark in FSP - <b>0: Auto(Default)</b>, 1: Enable,
- 2: Disable.
- 0:Auto, 1:Enable, 2:Disable
-**/
- UINT8 PanicWm;
-
-/** Offset 0x01EF - promoteMrcWarnings
- Enable or Disable MRC promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** promoteMrcWarnings
+ Determines if MRC warnings are promoted to system level in FSP.
+ $EN_DIS
**/
UINT8 promoteMrcWarnings;
-/** Offset 0x01F0 - promoteWarnings
- <b>Enable(Default)</b> or Disable Promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** promoteWarnings
+ Determines if warnings are promoted to system level in FSP.
+ $EN_DIS
**/
UINT8 promoteWarnings;
-/** Offset 0x01F1 - serialDebugMsgLvlTrainResults
- Enable or Disable Promote warning in FSP - <b>0:Disable(Default)</b>, 8:Enable.
- 0:Disable, 8:Enable
+/** serialDebugMsgLvlTrainResults
+ Enabled = set to display the training results. Training results also get displayed
+ if debug messages is set to Maximum in FSP.
+ $EN_DIS
**/
UINT8 serialDebugMsgLvlTrainResults;
-/** Offset 0x01F2 - MemTest
- <b>Enable(Default)</b> or Disable memory test during normal boot in FSP - 0: Disable,
- <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Enhanced Log Parsing
+ Enables additional output in debug log for easier machine parsing in FSP.
+ $EN_DIS
**/
- UINT8 HwMemTest;
+ UINT8 logParsing;
-/** Offset 0x01F3
+/** MemTest
+ Enable - Enables memory test during normal boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace8;
+ UINT8 HwMemTest;
-/** Offset 0x01F4 - MemTest Loops
- Number of memory test loops during normal boot, set to 0 to run memtest infinitely
- in FSP - <b> 1 (Default)</b>.
- minimum = 0, maximum = 65535
+/** MemTest Loops
+ Number of memory test loops during normal boot, set to 0 to run memtest infinitely in FSP.
**/
UINT16 MemTestLoops;
-/** Offset 0x01F6
-**/
- UINT8 UnusedUpdSpace9[2];
-
-/** Offset 0x01F8 - Adv MemTest Options
- This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16,
+/** Adv MemTest Options
+ This option is a bit mask[19:0]- All 0 = disabled- bit-0=XMATS8, bit-1=XMATS16,
bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
@@ -687,627 +668,1149 @@ typedef struct {
**/
UINT32 AdvMemTestOptions;
-/** Offset 0x01FC - SmartTestKey
+/** SmartTestKey
Number of SmartTest Key
**/
UINT32 SmartTestKey;
-/** Offset 0x0200 - Adv MemTest Pause
- Specify a pause delay between 0 to 256000 in units of usec. This is a time period
- where refresh is disabled between write and read sequences in FSP.
+/** Adv MemTest Pause
+ Specify a pause delay between 0 to 255 in units of msec. This is a time period where
+ refresh is disabled between write and read sequences in FSP.
**/
- UINT32 AdvMemTestCondPause;
+ UINT8 AdvMemTestCondPause;
-/** Offset 0x0204 - Adv MemTest tREFI
+/** Adv MemTest tREFI
Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
**/
UINT16 AdvMemTestCondTrefi;
-/** Offset 0x0206 - Adv MemTest tWR
- Specify tWR timing between 48 to 96 in units of tCK in FSP.
+/** Adv MemTest tWR
+ Specify tWR timing between 48 to 96 in units of tCK in FSP.
**/
UINT8 AdvMemTestCondTwr;
-/** Offset 0x0207
-**/
- UINT8 UnusedUpdSpace10;
-
-/** Offset 0x0208 - Adv MemTest PMIC VDD Level
+/** Adv MemTest PMIC VDD Level
Specify PMIC VDD level in units of mV in FSP.
**/
UINT16 AdvMemTestCondPmicVdd;
-/** Offset 0x020A - Adv MemTest Conditions
+/** Adv MemTest Conditions
Auto = set test conditions based on test type; Manual = specify global test conditions;
- Disable = Do not apply test conditions in FSP - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Manual.
+ Disable = Do not apply test conditions in FSP.
0:Disable, 1:Auto, 2:Manual
**/
UINT8 AdvMemTestCondition;
-/** Offset 0x020B - Adv MemTest Reset Failure Tracking List
+/** Adv MemTest Reset Failure Tracking List
Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
- Useful for testing performance of multiple options in FSP - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+ Useful for testing performance of multiple options in FSP.
+ $EN_DIS
**/
UINT8 AdvMemTestResetList;
-/** Offset 0x020C - MemTest On Cold Fast Boot
- Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
- Auto - Sets it to the MRC default setting; current default is Disable in FSP -
- <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 MemTestOnColdFastBoot;
-/** Offset 0x020D - Attempt Fast Boot
+/** Attempt Fast Boot
Enable - Portions of memory reference code will be skipped when possible to increase
- boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the
- MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+ boot speed on warm boots. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 AttemptFastBoot;
-/** Offset 0x020E - MemTest On Cold Fast Boot
- Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
- Auto - Sets it to the MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 AttemptFastBootCold;
-/** Offset 0x020F - Multithreaded Memory Training
- Selects the number of processor sockets to train in parallel. - <b>0: All sockets
- operate in parallel(Default)</b>. 1: At any time only one socket is executing.
- 2: At any time only two socket are executing. 4: At any time only four socket are
- executing in FSP.
+/** Multithreaded Memory Training
+ Selects the number of processor sockets to train in parallel. 0 - All sockets operate
+ in parallel. 1 - At any time only one socket is executing. 2 - At any time only
+ two socket are executing. 4 - At any time only four socket are executing in FSP.
0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
at a Time, 4:Four Sockets at a Time
**/
UINT8 AllowedSocketsInParallel;
-/** Offset 0x0210 - Auto-Reset on mem Training Error
- Enable/Disable Auto-Reset on mem Training Error in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** Auto-Reset on mem Training Error
+ Enable/Disable Auto-Reset on mem Training Error in FSP.
+ $EN_DIS
**/
UINT8 AutoResetOnMemErr;
-/** Offset 0x0211 - Rank Margin Tool
- Enable/Disable the Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Rank Margin Tool
+ Enable/Disable two types of rank margin in FSP.
+ 0:Normal RMT & Turnaround RMT Disabled, 1:Normal RMT Enabled, 2:Turnaround RMT Enabled,
+ 3:Normal RMT & Turnaround RMT Enabled, 4:Auto RMT Enable/Disabled
**/
UINT8 EnableRMT;
-/** Offset 0x0212 - RMT on Fast Cold Boot
- Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** RMT on Fast Cold Boot
+ Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP.
+ $EN_DIS
**/
UINT8 EnableRMTonFCB;
-/** Offset 0x0213 - Execute Jedecinit before RMT
- Execute Jedecinit before Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Execute Jedecinit before RMT
+ Execute Jedecinit before Rank Margin Tool in FSP.
+ $EN_DIS
**/
UINT8 JedecInitBeforeRMT;
-/** Offset 0x0214 - Backside Margining
- Enable/Disable margin test on the register or buffer backside in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** Backside Margining
+ Enable/Disable margin test on the register or buffer backside in FSP.
+ $EN_DIS
**/
UINT8 RMTBacksideMargining;
-/** Offset 0x0215 - CmdAll
- Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
- 1:Auto, 2:2, 4:4, 8:8
+/** CmdAll
+ Step size of CmdAll. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:1, 2:2, 4:4, 8:8
**/
UINT8 RMTCmdAll;
-/** Offset 0x0216 - RMT Debug Messages
- Enable/Disable the RMT debug messages in FSP - <b>2:Disable(Default)</b>, 5:Enable.
+/** RMT Debug Messages
+ Enable/Disable the RMT debug messages in FSP.
2:Disable, 5:Enable
**/
UINT8 RMTDebugMessages;
-/** Offset 0x0217 - RMT Display Tables
- Enable/Disable displaying results as tables in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Display Tables
+ Enable/Disable displaying results as tables in FSP.
+ $EN_DIS
**/
UINT8 RMTDisplayTables;
-/** Offset 0x0218 - RMT Loop Count
+/** RMT Loop Count
Exponential loop count for single rank test in FSP.
**/
UINT8 RMTLoopCount;
-/** Offset 0x0219
-**/
- UINT8 UnusedUpdSpace11[3];
-
-/** Offset 0x021C - Test Signal Bit Mask For RMT
+/** Test Signal Bit Mask For RMT
Test signal bit mask for RMT in FSP.
**/
UINT32 TestSignalBitMaskRMT;
-/** Offset 0x0220 - RMT Per Bit Margining
- Enable/Disable Per Bit Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per Bit Margining
+ Enable/Disable Per Bit Margining in FSP.
+ $EN_DIS
**/
UINT8 RMTPerBitMargining;
-/** Offset 0x0221 - RMT Per CA Lane Margining
- Enable/Disable Per CA Lane Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per CA Lane Margining
+ Enable/Disable Per CA Lane Margining in FSP.
+ $EN_DIS
**/
UINT8 RMTPerCaLaneMargining;
-/** Offset 0x0222 - RMT Display Plots
- Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per CS Lane Margining
+ Enable/Disable Per CS Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCsLaneMargining;
+
+/** RMT Display Plots
+ Enable/Disable the display of per-bit results as plots in FSP.
+ $EN_DIS
**/
UINT8 RMTPerDisplayPlots;
-/** Offset 0x0223 - RMT RxDqs
- Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
- 2:2, 4:4, 8:8.
+/** RMT RxDqs
+ Step size of RxDqs. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTRxDqs;
-/** Offset 0x0224 - RMT RxVref
- Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
- 2:2, 4:4, 8:8.
+/** RMT RxVref
+ Step size of RxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTRxVref;
-/** Offset 0x0225 - RMT Scrambler
- Enable or Disable scrambler during RMT test in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Dfx RMT Scrambler
+ Enable or Disable scrambler during RMT test in FSP.
+ $EN_DIS
**/
- UINT8 RMTScrambler;
+ UINT8 DfxScrambleEnRMT;
-/** Offset 0x0226 - RMT Step Size Override
- Enable or Disable overriding the default step sizes in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** RMT Step Size Override
+ Enable or Disable overriding the default step sizes in FSP.
+ $EN_DIS
**/
UINT8 RMTStepSizeOverride;
-/** Offset 0x0227 - RMT TxDq
- Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
+/** RMT TxDq
+ Step size of TxDq. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTTxDq;
-/** Offset 0x0228 - RMT TxVref
- Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
+/** RMT TxVref
+ Step size of TxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTTxVref;
-/** Offset 0x0229 - DDR5 ECS
- Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DDR5 ECS
+ Disable: Disable ECS/Result collection. Enable: Enable ECS without Result Collection.
+ Enable ECS with Result Collection: Enable ECS/Result Collection.
+ 0:Disable, 1:Enable, 2:Enable ECS with Result Collection
**/
UINT8 ErrorCheckScrub;
-/** Offset 0x022A - Enforce Memory POR
- 0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage
- programming. <b>2:Disable - Disables this feature and user is able to run at higher
- frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default)</b>.
- 0:Enforce POR, 2:Disabled
+/** Runtime PPR/Row Sparing
+ Enable/Disable Runtime PPR / Row Sparing.
+ $EN_DIS
+**/
+ UINT8 RtRowSparing;
+
+/** Mca Bank Warm Boot Clear Errors
+ Enable/Disable Mca Bank Warm Boot Clear Errors.
+ $EN_DIS
+**/
+ UINT8 McBankWarmBootClearError;
+
+/** RasStateVarPtr
+ Pointer to array of RAS_STATE_VARIABLE_DATA
+**/
+ UINT32 RasStateVarPtr;
+
+/** Enforce Memory POR
+ Enforce POR (0x0) - Enforces Plan Of Record restrictions for DDR5 frequency and
+ voltage programming. Enforce Stretch Goals (0x1) - Enforce DDR memory frequency
+ stretch goal. <b>Disable (0x2 - Default)</b> - Disables this feature and user is
+ able to run at higher frequencies, specified in the DDR Frequency Limit field (limited
+ by processor support).
+ 0:POR, 1:Enforce Stretch Goals, 2:Disabled
**/
UINT8 EnforceDdrMemoryFreqPor;
-/** Offset 0x022B - Enforce Population POR
+/** Enforce Population POR
Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations
- will only allow populations that have been validated in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+ will only allow populations that have been validated in FSP.
+ $EN_DIS
**/
UINT8 EnforcePopulationPor;
-/** Offset 0x022C - DDR PPR Type
- Selects DDR Post Package Repair Type - 2: Hard PPR, <b>1: Soft PPR (Default)</b>,
- 0: Disabled.
+/** DDR PPR Type
+ Selects DDR Post Package Repair Type - 2- Hard PPR, <b>1- Soft PPR (Default)</b>,
+ 0- Disabled.
0:Disabled, 2:Hard PPR, 1:Soft PPR
**/
UINT8 pprType;
-/** Offset 0x022D - Force PPR On All Dram for UCE
- Force PPR on all dram for UCE in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disabled, 1:Enabled
-**/
- UINT8 ForcePprOnAllDramUce;
-
-/** Offset 0x022E
-**/
- UINT8 UnusedUpdSpace12[2];
-
-/** Offset 0x0230 - pprAddrVariablePtr
+/** pprAddrVariablePtr
Pointer to array of PPR_ADDR_VARIABLE
**/
UINT32 PprAddrVariablePtr;
-/** Offset 0x0234 - Allow Memory Test Correctable Error
+/** BDAT ACPI Table
+ Enable / Disable publishing BDAT ACPI Table in FSP.
+ $EN_DIS
+**/
+ UINT8 bdatEn;
+
+/** Allow Memory Test Correctable Error
Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
- default setting; current default is Enable in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+ default setting; current default is Enable in FSP.
+ $EN_DIS
**/
UINT8 allowCorrectableMemTestError;
-/** Offset 0x0235 - Memory I/O Health Check
- Memory I/O Health Check - 0: Auto, 1: Manual, <b>2: Disable (Default)</b>. Select
- option Auto for default values. Manual for new values. Disable for disabling feature
- in FSP - 0:Auto, 1:Manual, <b>2:Disable(Default)</b>.
+/** SlotPerChannel
+ Slot number per channel, default value is 2
+ 1:Slot1, 2:Slot2
+**/
+ UINT8 SlotPerChannel;
+
+/** Memory I/O Health Check
+ Memory I/O Health Check - 0- Auto, 1- Manual, <b>2- Disable (Default)</b>. Select
+ option Auto for default values. Manual for new values. Disable for disabling feature in FSP.
0:Auto, 1:Manual, 2:Disable
**/
UINT8 MemIOHealthCheck;
-/** Offset 0x0236 - RxDqsDelay Left Edge
+/** Memory I/O Health Turnaround Test
+ Memory I/O Health Turnaround Test - 1- Enable, <b>0- Disable (Default)</b>. Select
+ Disable for disabling feature in FSP. Enable for enabling feature in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemIOHealthTurnaroundTest;
+
+/** Memory I/O Health Check Loop Count
+ CPGC Test Loop Count for Memory IO Health Test.
+**/
+ UINT8 MemIOLoopCount;
+
+/** RxDqsDelay Left Edge
Offset for RxDqsDelay Left Edge in FSP.
**/
UINT8 CriticalRxDqsDelayLeftEdge;
-/** Offset 0x0237 - RxDqsDelay Right Edge
+/** RxDqsDelay Right Edge
Offset for RxDqsDelay Right in FSP.
**/
UINT8 CriticalRxDqsDelayRightEdge;
-/** Offset 0x0238 - RxVref Left Edge
+/** RxVref Left Edge
Offset for RxVref Left Edge in FSP.
**/
UINT8 CriticalRxVrefLeftEdge;
-/** Offset 0x0239 - RxVref Right Edge
+/** RxVref Right Edge
Offset for RxVref Right Edge in FSP.
**/
UINT8 CriticalRxVrefRightEdge;
-/** Offset 0x023A - TxDqDelay Left Edge
+/** TxDqDelay Left Edge
Offset for TxDqDelay Left Edge in FSP.
**/
UINT8 CriticalTxDqDelayLeftEdge;
-/** Offset 0x023B - TxDqDelay Right Edge
+/** TxDqDelay Right Edge
Offset for TxDqDelay Right Edge in FSP.
**/
UINT8 CriticalTxDqDelayRightEdge;
-/** Offset 0x023C - TxVref Left Edge
+/** TxVref Left Edge
Offset for TxDqDelay Left Edge in FSP.
**/
UINT8 CriticalTxVrefLeftEdge;
-/** Offset 0x023D - TxVref Right Edge
+/** TxVref Right Edge
Offset for TxDqDelay Right Edge in FSP.
**/
UINT8 CriticalTxVrefRightEdge;
-/** Offset 0x023E - Reboot On Critical Failure
- Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Reboot On Critical Failure
+ Reboot System on Critical failure to do Memory Training in FSP.
+ $EN_DIS
**/
UINT8 ResetOnCriticalError;
-/** Offset 0x023F - Number of Times to Reboot and Retrain
+/** Number of Times to Reboot and Retrain
Number of times to Reboot System on Critical failure to do Memory Training in FSP.
**/
UINT8 CriticalRetries;
-/** Offset 0x0240 - Memory I/O Health Check Loop Count
- CPGC Test Loop Count for Memory IO Health Test
-**/
- UINT8 MemIOHealthLoopCount;
-
-/** Offset 0x0241 - Telemetry RxDqsDelay Left Edge
+/** Telemetry RxDqsDelay Left Edge
Offset for Telemetry RxDqsDelay Left Edge in FSP.
**/
UINT8 TelemetryRxDqsDelayLeftEdge;
-/** Offset 0x0242 - Telemetry RxDqsDelay Right Edge
+/** Telemetry RxDqsDelay Right Edge
Offset for Telemetry RxDqsDelay Right Edge in FSP.
**/
UINT8 TelemetryRxDqsDelayRightEdge;
-/** Offset 0x0243 - Telemetry RxVref Left Edge
+/** Telemetry RxVref Left Edge
Offset for Telemetry RxDqsDelay Left Edge in FSP.
**/
UINT8 TelemetryRxVrefLeftEdge;
-/** Offset 0x0244 - Telemetry RxVref Right Edge
+/** Telemetry RxVref Right Edge
Offset for Telemetry RxDqsDelay Right Edge in FSP.
**/
UINT8 TelemetryRxVrefRightEdge;
-/** Offset 0x0245 - Telemetry TxDqDelay Left Edge
+/** Telemetry TxDqDelay Left Edge
Offset for Telemetry TxDqDelay Left Edge in FSP.
**/
UINT8 TelemetryTxDqDelayLeftEdge;
-/** Offset 0x0246 - Telemetry TxDqDelay Right Edge
+/** Telemetry TxDqDelay Right Edge
Offset for Telemetry TxDqDelay Right Edge in FSP.
**/
UINT8 TelemetryTxDqDelayRightEdge;
-/** Offset 0x0247 - Volatile Memory Mode
- Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try
- to configure 2LM but if system is unable to configure 2LM, volatile memory mode
- will fall back to 1LM in FSP - <b>0: 1LM(Default)</b>, 1: 2LM, 2: MIX 1LM2LM.
- 0: 1LM, 1: 2LM, 2: MIX 1LM2LM
+/** Telemetry TxVref Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefLeftEdge;
+
+/** Telemetry TxVref Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefRightEdge;
+
+/** Telemetry CaTiming Left Edge
+ Offset for Telemetry CaTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingLeftEdge;
+
+/** Telemetry CaTiming Right Edge
+ Offset for Telemetry CaTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingRightEdge;
+
+/** Telemetry CtlTiming Left Edge
+ Offset for Telemetry CtlTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingLeftEdge;
+
+/** Telemetry CtlTiming Right Edge
+ Offset for Telemetry CtlTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingRightEdge;
+
+/** Telemetry CaVref Left Edge
+ Offset for Telemetry CaVref Left Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefLeftEdge;
+
+/** Telemetry CaVref Right Edge
+ Offset for Telemetry CaVref Right Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefRightEdge;
+
+/** Critical CaTiming Left Edge
+ Offset for Critical CaTiming Left Edge in FSP.
**/
- UINT8 volMemMode;
+ UINT8 CriticalCaTimingLeftEdge;
-/** Offset 0x0248 - Dynamic ECC Mode Selection
- Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, <b>1:Enable(Default)</b>,
- 2:Enable + Allow 128b ECC.
- 0:Disable, 1:Enable, 2:Enable + Allow 128b ECC
+/** Critical CaTiming Right Edge
+ Offset for Critical CaTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCaTimingRightEdge;
+
+/** Critical CtlTiming Left Edge
+ Offset for Critical CtlTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingLeftEdge;
+
+/** Critical CtlTiming Right Edge
+ Offset for Critical CtlTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingRightEdge;
+
+/** Critical CaVref Left Edge
+ Offset for Critical CaVref Left Edge in FSP.
+**/
+ UINT8 CriticalCaVrefLeftEdge;
+
+/** Critical CaVref Right Edge
+ Offset for Critical CaVref Right Edge in FSP.
+**/
+ UINT8 CriticalCaVrefRightEdge;
+
+/** Intel(R) Flat Memory Mode Support
+ Enable or disable Intel(R) Flat Memory Mode support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Flat2lmSupport;
+
+/** Dynamic ECC Mode Selection
+ Enable/Disable Dynamic ECC Mode Selection in FSP.
+ $EN_DIS
**/
UINT8 DynamicEccModeSel;
-/** Offset 0x0249 - Memory Patrol Scrub
- Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), <b>2:Enable during
- NotifyPhase(EnumInitPhaseReadyToBoot) (Default)</b>.
- 0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot
+/** Leaky bucket high bit
+ Leaky bucket high bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktHi;
+
+/** Leaky bucket time window based interface Hour
+ Leaky bucket time window based interface Hour" (0 - 24)
+**/
+ UINT16 leakyBktHour;
+
+/** Leaky bucket low bit
+ Leaky bucket low bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktLo;
+
+/** Leaky bucket time window based interface Minute
+ Leaky bucket time window based interface Minute" (0 - 60)
+**/
+ UINT8 leakyBktMinute;
+
+/** Leaky bucket time window based interface
+ Enable/Disable leaky bucket time window based interface
+ 0:Disable, 1:Enable
+**/
+ UINT8 leakyBktTimeWindow;
+
+/** Memory Patrol Scrub
+ Enable/Disable Patrol Scrub
+ 0:Disable, 2:Enable at End of POST
**/
UINT8 PatrolScrub;
-/** Offset 0x024A - Memory Patrol Scrub
+/** Memory Patrol Scrub Notify
Memory Patrol Scrub - <b>0:Disable (Default)</b>, 1:Enable at ReadyToBootFsp().
- 0:Disable, 1:Enable Enable at ReadyToBootFsp()
+ 0:Disable, 1:Enable at ReadyToBootFsp()
**/
UINT8 PatrolScrubNotify;
-/** Offset 0x024B - Patrol Scrub Interval
+/** Patrol Scrub Interval
Patrol Scrub Interval in FSP.
**/
UINT8 PatrolScrubDuration;
-/** Offset 0x024C - Patrol Scrub Address Mode
- Selects the address mode between <b>1: System Physical Address (Default)</b>, 0:Reverse
- Address in FSP.
+/** Patrol Scrub Address Mode
+ Selects the address mode between <b>System Physical Address (0x1 - Default)</b>
+ or Reverse Address (0x0) in FSP.
0:Reverse Address, 1:System Physical Address
**/
UINT8 PatrolScrubAddrMode;
-/** Offset 0x024D - Memory Thermal Throttling Mode
- Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, <b>2:CLTT_ENABLE(Default)</b>,
- 3:CLTT_PECI_ENABLE.
- 0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE
+/** Memory Thermal Throttling Mode
+ Memory Configure Memory Thermal Throttling Mode in FSP.
+ 0:Disable, 2:CLTT, 3:CLTT with PECI
**/
UINT8 thermalthrottlingsupport;
-/** Offset 0x024E - Memory Correctable Error Threshold
+/** Memory Correctable Error Threshold
Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
**/
UINT16 spareErrTh;
-/** Offset 0x0250 - WR CRC feature Control
- Enable/Disable Write CRC in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** WR CRC feature Control
+ Enable/Disable Write CRC in FSP.
+ $EN_DIS
**/
UINT8 WrCRC;
-/** Offset 0x0251 - Adaptive Refresh Management Level
+/** DDR 2x Refresh Enable
+ Enable/Disable 2x Refresh. Auto = dynamically selected.
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 RefreshMode;
+
+/** Adaptive Refresh Management Level
Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
- required. <b>0:Default - RAAIMT, RAAMMT, RAADEC(Default)</b>; 1:Level A - RAAIMT-A,
- RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C,
- RAAMMT-C, RAADEC-C
- 0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level
- B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C
+ required. 0:Default - RAAIMT, RAAMMT, RAADEC; 1:Level A - RAAIMT-A, RAAMMT-A, RAADEC-A;
+ 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, RAAMMT-C, RAADEC-C
+ 0:Default - RAAIMT or RAAMMT or RAADEC, 1:Level A - RAAIMT-A or RAAMMT-A or RAADEC-A,
+ 2:Level B - RAAIMT-B or RAAMMT-B or RAADEC-B, 3:Level C - RAAIMT-C or RAAMMT-C
+ or RAADEC-C
**/
UINT8 AdaptiveRefreshMgmtLevel;
-/** Offset 0x0252 - MEMHOT INPUT Control
- Enable/Disable MEMHOT INPUT in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** CXL Hetero Support
+ Enable/Disable (Default) DDR CXL Heterogeneous Interleave in FSP.
+ $EN_DIS
**/
- UINT8 MemHotIn;
+ UINT8 CxlHeteroSupport;
-/** Offset 0x0253 - MEMHOT OUTPUT Mode
- MEMHOT OUTPUT Mode in FSP - 0:Disable, <b>1:Enable only temphi(Default)</b>, 2:Enable
- temphi & mid, 3:Enable temphi & mid & low.
- 0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low
+/** MEMHOT INPUT Control
+ Enable/Disable MEMHOT INPUT in FSP.
+ $EN_DIS
**/
- UINT8 MemhotOutputOnlyOpt;
+ UINT8 MemHotIn;
-/** Offset 0x0254 - CxlType3LegacyEn
- Enable or disable CXL type 3 device using CXL type 2 flow - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** MEMHOT OUTPUT Mode
+ MEMHOT OUTPUT Mode in FSP.
+ 0:Disable, 1:Enable only temphi, 2:Enable only temphi and mid, 3:Enable only temphi
+ mid and low
**/
- UINT8 DfxCxlType3LegacyEn;
+ UINT8 MemhotOutputOnlyOpt;
-/** Offset 0x0255 - DfxPmicSecureMode
- 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, <b>2:Auto Pmic Secure Mode(Default)</b>.
+/** DfxPmicSecureMode
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode.
0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
**/
UINT8 DfxPmicSecureMode;
-/** Offset 0x0256 - IIO PcieSubSystemMode0
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode0[8];
-
-/** Offset 0x025E - IIO PcieSubSystemMode1
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode1[8];
-
-/** Offset 0x0266 - IIO PcieSubSystemMode2
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+/** SpdPrintEn
+ Enable/Disable SPD Print
+ $EN_DIS
**/
- UINT8 IioPcieSubSystemMode2[8];
+ UINT8 SpdPrintEn;
-/** Offset 0x026E - IIO PcieSubSystemMode3
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode3[8];
-
-/** Offset 0x0276 - IIO PcieSubSystemMode4
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode4[8];
-
-/** Offset 0x027E - IIO PcieSubSystemMode5
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode5[8];
-
-/** Offset 0x0286 - IIO PcieSubSystemMode6
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+/** Force PPR On All Dram For UCE
+ Enable/Disable force PPR on all dram for UCE.
+ 0:Disable, 1:Enable
**/
- UINT8 IioPcieSubSystemMode6[8];
+ UINT8 ForcePprOnAllDramUce;
-/** Offset 0x028E - CXL Header Bypass
- Enable/Disable the CXL header bypass in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
+/** CXL Header Bypass
+ Enable/Disable the CXL header bypass in FSP.
0:Disable, 1:Enable
**/
UINT8 DfxCxlHeaderBypass;
-/** Offset 0x028F - CXL Security Level
+/** CXL Security Level
CXL Security Level<br>\n
- 0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
+ 0- Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
attached memory ranges in the WB address space.<br>\n
- 1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
+ 1- Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
ranges only;<br>\n
- 2: Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
- <b>3: Auto - Currently identical to Fully Trusted. (Default)</b>
+ 2- Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
+ <b>3- Auto - Currently identical to Fully Trusted. (Default)</b>
0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
**/
UINT8 DfxCxlSecLvl;
-/** Offset 0x0290
-**/
- UINT32 DfxCxlDebugModePtr;
-
-/** Offset 0x0294
-**/
- UINT32 DfxCxlDebugModeNumber;
-
-/** Offset 0x0298 - Lock Chipset
- Lock or Unlock chipset in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** CXL VID
+ CXL VID on SPR B0. Auto(Default) and Enable is 0x1E98. Disable is 0x8086
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 LockChipset;
+ UINT8 DfxCxlVid;
-/** Offset 0x0299 - MSR Lock Control
- Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
- remove lock bits - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** Warm-Reset Elimination
+ When enabled, BIOS will attempt to skip warm-reset on the cold-reset path. Auto:
+ platform or silicon RC policy determines feature status
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 ProcessorMsrLockControl;
+ UINT8 DfxWarmResetEliminationEn;
-/** Offset 0x029A - DFX Enable
- When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - <b>0:Disabled(Default)</b>,
- 1:Enabled.
- 0:Disable, 1:Enable
+/** IIO DFX CxlDebugMode Ptr
+ Pointer to array of CxlDebugMode settings Per Port, 0x00000000 indicates Dfx CXL
+ Debug mode Disable.
**/
- UINT8 DFXEnable;
+ UINT32 DfxCxlDebugModePtr;
-/** Offset 0x029B - DFX Disable Bios Done
- When Enabled, suppresses notifying processor via MSR 151h that boot initialization
- is finished in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** IIO DFX CxlDebugMode Number
+ Number of elements in DfxCxlDebugModePtr array, port number as unit, should be set
+ along with DfxCxlDebugModePtr.
**/
- UINT8 DfxDisableBiosDone;
+ UINT32 DfxCxlDebugModeNumber;
-/** Offset 0x029C - Processor Package C State
- Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
+/** Processor Package C State
+ Package C State 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
state, 7: No Limit, <b>0xFF: Auto (Default)</b>
0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
7: No Limit, 0xFF: Auto
**/
UINT8 CpuPmPackageCState;
-/** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech
- Enhanced Intel SpeedStep(R) Tech - <b>1: Enable(Default)</b>, 0: Disable.
- 0:Disabled, 1:Enabled
+/** Enhanced Intel SpeedStep(R) Tech
+ Enable(Default)/Disable Enhanced Intel SpeedStep(R) Tech
+ $EN_DIS
**/
UINT8 CpuPmEistEnable;
-/** Offset 0x029E - C1E
- C1E - <b>1: Enable(Default)</b>, 0: Disable.
+/** C1E
+ Enable(Default)/Disable C1E
+ $EN_DIS
**/
UINT8 CpuPmC1eEnable;
-/** Offset 0x029F - Intel SST-PP
- Intel SST-PP Select allows user to choose level - <b>0xFF: Choose lowest level hardware
- supported(Default)</b>, 0: Level 0, 3: Level 3, 4: Level 4.
+/** Intel SST-PP
+ Intel SST-PP Select allows user to choose level.\n
+ AUTO: Choose lowest level hardware supported.
+ 0xFF: AUTO (default), 0: Level 0, 1: Level 1, 2: Level 2, 3: Level 3, 4: Level 4
**/
- UINT8 CpuPmIssTdpLevel;
+ UINT8 CpuPmSstPpLevel;
-/** Offset 0x02A0 - Activate SST-BF
+/** Intel SST-BF
SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
- 0:Disabled, 1:Enabled
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorSstBfSetting;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die0;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die1;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die2;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die0;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die1;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die2;
+
+/** Processor Dynamic Intel Speed Select (ISS) Function
+ Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function
+ $EN_DIS
+**/
+ UINT8 CpuPmDynamicIss;
+
+/** BIOS Region Base
+ Pointer to the location of the BIOS Region
**/
- UINT8 CpuPmProcessorActivePbf;
+ UINT32 BiosRegionBase;
-/** Offset 0x02A1
+/** BIOS Region Size
+ The size of the BIOS Region in bytes
**/
- UINT8 UnusedUpdSpace13[7];
+ UINT32 BiosRegionSize;
-/** Offset 0x02A8 - Socket 0 Core Disable Bitmask
- Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core
- disabled by user will force static SST-PP.
+/** Platform Data Area Base
+ Pointer to the location of the Platform Data Area
**/
- UINT64 CpuPmCoreDisableBitmask0;
+ UINT32 PlatformDataAreaBase;
-/** Offset 0x02B0 - Socket 1 Core Disable Bitmask
- Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core
- disabled by user will force static SST-PP.
+/** Platform Data Area Size
+ The size of the Platform Data Area in bytes
**/
- UINT64 CpuPmCoreDisableBitmask1;
+ UINT32 PlatformDataAreaSize;
-/** Offset 0x02B8
+/** N/A
**/
UINT8 ReservedMemoryInitUpd[16];
-/** IIO Board settings Hob Ptr
- Pointer to array of IIO_BOARD_SETTINGS_HOB
+/** Enable TME
+ Enable TME
+ $EN_DIS
**/
- UINT32 IioBoardSettingsHobPtr;
+ UINT8 SecurityCctEnableTme;
-/** IIO Board Settings Hob length
- The IIO Board Settings Hob Length.
+/** Enable TME CR
+ Enable TME CR
+ $EN_DIS
**/
- UINT32 IioBoardSettingsHobLength;
+ UINT8 SecurityCctEnableTmeCR;
-/** BIOS Region Base
- Pointer to the location of the BIOS Region
+/** Enable MKTME
+ Enable MKTME
+ $EN_DIS
**/
- UINT32 BiosRegionBase;
-
-/** BIOS Region Size
- The size of the BIOS Region in bytes
+ UINT8 SecurityCctEnableMktme;
+
+/** Enable Global Integrity
+ Enable Global Integrity
+ $EN_DIS
**/
- UINT32 BiosRegionSize;
+ UINT8 SecurityCctEnableGlobalIntegrity;
+
+/** Select TME Crypto Algorithm
+ Enable Global Integrity
+ 0:Algo1,1:Algo2, 2:Algo3
+**/
+ UINT16 SecurityCctTmeCryptoAlg;
+
+/** Enable TDX
+ : Enable TDX
+**/
+ UINT8 SecurityCctEnableTdx;
+
+/** Enable TDX Connect
+ : Enable TDX Connect
+**/
+ UINT8 SecurityCctEnableTdxConnect;
+
+/** TDX Physical PCIe Port Disable Bitmap
+ TDX Physical PCIe Port Disable Bitmap
+**/
+ UINT16 SecurityCctTdxPhysicalPciePortDisableBitmap[8];
+
+/** Key Split
+ : Key Split
+**/
+ UINT8 SecurityCctKeySplit;
+
+/** Enable TDX SEAM Loader
+ : Enable TDX SEAM Loader
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxSeamldr;
+
+/** Enabne SGX
+ : Enable SGX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSgx;
+
+/** Dfx Sgx CMCS Payload
+ Dfx Sgx CMCS Payload
+**/
+ UINT64 SecurityCctDfxSgxCmcsPayload[16];
+
+/** SGX QoS
+ : SGX QoS
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxQoS;
+
+/** SGX Auto Registration Agent
+ : SGX Auto Registration Agent
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxAutoRegistrationAgent;
+
+/** SGX Package Info In Band Access
+ : SGX Package Info In Band Access
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxPackageInfoInBandAccess;
+
+/** EPOCH Update
+ : EPOCH Update
+ 3:EpochDeactived, 0:EpochActived, 1:NewRandomEpoch, 2:ManualEpoch
+**/
+ UINT8 SecurityCctEpochUpdate;
+
+/** SGX EPOCH 0
+ : SGX EPOCH 0
+**/
+ UINT64 SecurityCctSgxEpoch0;
+
+/** SGX EPOCH 1
+ : SGX EPOCH 1
+**/
+ UINT64 SecurityCctSgxEpoch1;
+
+/** SGX LeWr
+ : SGX LeWr
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxLeWr;
+
+/** SGX Le Public Key Hash 0
+ : SGX Le Public Key Hash 0
+**/
+ UINT64 SecurityCctSgxLePubKeyHash0;
+
+/** SGX Le Public Key Hash 1
+ : SGX Le Public Key Hash 1
+**/
+ UINT64 SecurityCctSgxLePubKeyHash1;
+
+/** SGX Le Public Key Hash 2
+ : SGX Le Public Key Hash 2
+**/
+ UINT64 SecurityCctSgxLePubKeyHash2;
+
+/** SGX Le Public Key Hash 3
+ : SGX Le Public Key Hash 3
+**/
+ UINT64 SecurityCctSgxLePubKeyHash3;
+
+/** SGX Debug Mode
+ : SGX Debug Mode
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxDebugMode;
+
+/** SGX Factory Reset
+ : SGX Factory Reset
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxFactoryReset;
+
+/** Dfx Bios Param Header Override
+ : Dfx Bios Param Header Override
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxBiosParamHeaderOverride;
+
+/** Dfx Bios Param Header Version
+ : Dfx Bios Param Header Version
+**/
+ UINT16 SecurityCctDfxBiosParamHeaderVersion;
+
+/** Dfx Disable Actm Launch
+ : Dfx Disable Actm Launch
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxDisableActmLaunch;
+
+/** ACTM Flash Base
+ : ACTM Flash Base
+**/
+ UINT32 SecurityCctActmPcdFlash;
+
+/** Enable UPI FLE
+ : Enable UPI FLE
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableUpiFle;
+
+/** Enable SAF
+ : Enable SAF
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSaf;
+
+/** Dfx TDX Disable 1MB CMR Exclude
+ : Dfx TDX Disable 1MB CMR Exclude
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxTdxDisable1MbCmrExclude;
+
+/** Dfx Seamldr Source location
+ : Dfx Seamldr Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxSeamldrSrc;
+
+/** Dfx Tdx module Source location
+ : Dfx Tdx module Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxTdxModuleSrc;
+
+/** Dfx PRMRR SEAMRR Support
+ : Dfx PRMRR SEAMRR Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxPrmrrSeamrrSupport;
+
+/** Dfx Simics Environment
+ : Dfx Simics Environment
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSimicsEnvironment;
+
+/** Dfx Force UPL Unsupported
+ : Dfx Force UPL Unsupported
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxForceUplUnsupported;
+
+/** Dfx TME Key Restore
+ : Dfx TME Key Restore
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxTmeKeyRestore;
+
+/** Dfx TME Exclusion Base
+ : Dfx TME Exclusion Base
+**/
+ UINT64 SecurityCctDfxTmeExclusionBase;
+
+/** Dfx TME Exclusion Length
+ : Dfx TME Exclusion Length
+**/
+ UINT64 SecurityCctDfxTmeExclusionLength;
+
+/** Dfx MKTME KeyIdBits Override
+ : Dfx MKTME KeyIdBits Override
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverride;
+
+/** Dfx MKTME KeyIdBits Override Value
+ : Dfx MKTME KeyIdBits Override Value
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverrideValue;
+
+/** Dfx SGX Debug Print
+ : Dfx SGX Debug Print
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxDebugPrint;
+
+/** Dfx SGX Registration Server Select
+ : Dfx SGX Registration Server Select
+ 1:PRX, 0:SBX, 3:LIV, 4:SoftwareDefined, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxRegistrationServerSelect;
+
+/** Dfx SGX Add Package Support
+ : Dfx SGX Add Package Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxAddPackageSupport;
+
+/** Dfx allow SGX non POR memory population
+ : Dfx SGX Add Package Support
+ 1:Enabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxAllowSgxNonPorMemoryPopulation;
+
+/** Dfx SGX Hang Before ACTM
+ : Dfx SGX Hang Before ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeActm;
+
+/** Dfx SGX Hang After ACTM
+ : Dfx SGX Hang After ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterActm;
+
+/** Dfx SGX Hang Before MCHECK
+ : Dfx SGX Hang Before MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMcheck;
+
+/** Dfx SGX Hang After MCHECK
+ : Dfx SGX Hang After MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMcheck;
+
+/** Dfx SGX Hang Before MSR 7A
+ : Dfx SGX Hang Before MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMsr7a;
+
+/** Dfx SGX Hang After MSR 7A
+ : Dfx SGX Hang After MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMsr7a;
+
+/** Dfx disable CCT MSR_BIOS_DONE
+ : Dfx disable CCT MSR_BIOS_DONE
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxDisableCctBiosDone;
+
+/** Dfx Mcheck MSR 72
+ : Dfx Mcheck MSR 72 programming
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMcheckMsr72;
+
+/** Dfx Skip Warm Reset Promotion
+ : Dfx Skip Warm Reset Promotion
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSkipWarmResetPromotion;
+
+/** Enable SBFT
+ : Enable SBFT
+ 1:Enabled, 0:Disabled, 4:IfsSbftSgxEnabled
+**/
+ UINT8 SecurityCctEnableSbft;
+
+/** PRMRR SGX Size
+ : PRMRR SGX Size
+ 0x8000000:128MB, 0x10000000:256MB, 0x20000000:512MB, 0x40000000:1GB, 0x80000000:2GB,
+ 0x100000000:4GB, 0x200000000:8GB,0x400000000:16GB, 0x800000000:32GB, 0x1000000000:64GB,
+ 0x2000000000:128GB, 0x4000000000:256GB, 0x8000000000:512GB
+**/
+ UINT64 SecurityCctPrmrrSgxSize;
+
+/** PRMRR SAF Size
+ : PRMRR SAF Size
+ 0x0:Invalid, 0x800000:8MB, 0x2000000:32MB, 0x4000000:64MB, 0x8000000:128MB, 0x10000000:256MB
+**/
+ UINT64 SecurityCctPrmrrSafSize;
+
+/** PRMRR SBFT Size
+ : PRMRR SBFT Size
+ 0x0:Invalid, 0x10000000:256MB, 0x20000000:512MB
+**/
+ UINT64 SecurityCctPrmrrSbftSize;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** SINIT ACM SE SVN default
+ Default value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnFspDefault;
+
+/** SINIT ACM SE SVN override request
+ Override request for SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnOverrideRequest;
+
+/** SINIT ACM SE SVN value
+ Value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnValue;
+
+/** Setup data pointer
+ : Setup data pointer
+**/
+ UINT64 SetupDataPtr;
+
+/** Setup data Size
+ : Setup data Size
+**/
+ UINT64 SetupDataSize;
+
+/** Emulation Setting data pointer
+ : Emulation Setting data pointer
+**/
+ UINT64 EmulationSettingPtr;
+
+/** Emulation Setting data Size
+ : Emulation Setting data Size
+**/
+ UINT64 EmulationSettingSize;
+
+/** Platform info data pointer
+ : Platform info data pointer
+**/
+ UINT64 PlatformInfoPtr;
+
+/** Platform info data Size
+ : Platform info data Size
+**/
+ UINT64 PlatformInfoSize;
+
+/** FSPM Upd settings support
+ : FSPM Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspmUpdSupport;
+
+/** Gen4 RCD Dimm support
+ Gen4 RCD Dimm support, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen4RcdDeviceSupport;
} FSPM_CONFIG;
+
typedef struct {
-
+
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
/** N/A
**/
FSPM_ARCH2_UPD FspmArchUpd;
-
+
/** N/A
**/
FSPM_CONFIG FspmConfig;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h
index 864a5a983f..11628ff7ee 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -30,261 +30,224 @@ are permitted provided that the following conditions are met:
**/
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
+#ifndef __FSPS_UPD_H__
+#define __FSPS_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
-
-/** FSP-S Configuration
-**/
typedef struct {
-/** Offset 0x0020 - Processor VmxEnable Function
- Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
- 0: Disable, 1: Enable
+/** PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
**/
- UINT8 VmxEnable;
+ UINT8 EnablePcie0;
-/** Offset 0x0021 - Processor TurboMode Function
- Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
- 0: Disable, 1: Enable
+/** PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
**/
- UINT8 TurboMode;
+ UINT8 EnablePcie1;
-/** Offset 0x0022 - Processor Safer Mode Extensions Function
- Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
- Processor Safer Mode Extensions Function.
- 0: Disable, 1: Enable
+/** Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
**/
- UINT8 ProcessorSmxEnable;
+ UINT8 EnableEmmc;
-/** Offset 0x0023 - SstCp
- SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
- 0: Disable, 1: Enable
+/** LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
- UINT8 SstCpSetting;
+ UINT8 EnableGbE;
-/** Offset 0x0024 - SstCp Capable Status
- SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
- 0: Disable, 1: Enable
+/** PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 SstCpCapableSystem;
+ UINT8 PcieRootPort0DeEmphasis;
-/** Offset 0x0025
+/** PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 UnusedUpdSpace0[1];
+ UINT8 PcieRootPort1DeEmphasis;
-/** Offset 0x0026 - PCH Protect Range Limit
- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
- limit comparison.
+/** PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT16 PchProtectedRangeLimit[5];
-
-/** Offset 0x0030 - PCH Protect Range Base
- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
- UINT16 PchProtectedRangeBase[5];
+ UINT8 PcieRootPort2DeEmphasis;
-/** Offset 0x003A - PchAdrEn
- PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
- 0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
+/** PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 PchAdrEn;
+ UINT8 PcieRootPort3DeEmphasis;
-/** FSP smm init enable
- Enable / Disable FSP smm init
- $EN_DIS
+/** PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 FspSmmInitEn;
+ UINT8 PcieRootPort4DeEmphasis;
-/** Offset 0x003B - EnableTme
- EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
- 0: Disabled, 1: Enabled, 2:Software Controlled
+/** PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 EnableTme;
+ UINT8 PcieRootPort5DeEmphasis;
-/** Offset 0x003C - EnableTmeBypass
- EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 EnableTmeBypass;
+ UINT8 PcieRootPort6DeEmphasis;
-/** Offset 0x003D - SgxFactoryReset
- SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 SgxFactoryReset;
+ UINT8 PcieRootPort7DeEmphasis;
-/** Offset 0x003E - EnableSgx
- EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** eMMC DLL Configuration Data
+ Pointer to eMMC DLL Configuration Data
**/
- UINT8 EnableSgx;
+ UINT32 EMMCDLLConfigPtr;
-/** Offset 0x003F - SgxPackageInfoInBandAccess
- SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
**/
- UINT8 SgxPackageInfoInBandAccess;
+ UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x0040 - SgxQoS
- SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
- 0: Disabled, 1: Enabled
+/** PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
- UINT8 SgxQoS;
+ UINT16 PchProtectedRangeBase[5];
-/** Offset 0x0041 - EpochUpdate
- EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
- EPOCHs(Default)</b>.
- 1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
+/** PchAdrEn
+ PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
+ 0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
**/
- UINT8 EpochUpdate;
+ UINT8 PchAdrEn;
-/** Offset 0x0042 - SgxLeWr
- SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** Enable Timed GPIO0
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
**/
- UINT8 SgxLeWr;
+ UINT8 EnableTimedGpio0;
-/** Offset 0x0043 - SgxDebugMode
- SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** Enable Timed GPIO1
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
**/
- UINT8 SgxDebugMode;
+ UINT8 EnableTimedGpio1;
-/** Offset 0x0044 - SgxAutoRegistrationAgent
- SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** FSP smm init enable
+ Enable / Disable FSP smm init
+ $EN_DIS
**/
- UINT8 SgxAutoRegistrationAgent;
+ UINT8 FspSmmInitEn;
-/** Offset 0x0045 - DfxSgxRegistrationServerSelect
- DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
- 4:SW Defined Server.
- 0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
+/** C2C3TT
+ Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
+ 0: Default, Bit[11:0] : C2 to C3 Transition Timer
**/
- UINT8 DfxSgxRegistrationServerSelect;
+ UINT8 CpuPmC2c3tt;
-/** Offset 0x0046 - Processor Enable Monitor MWAIT
- Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
- Monitor MWAIT.
- 0: Disabled, 1: Enabled
+/** Processor Enable Monitor MWAIT
+ Enable(Default) or Disable Processor Monitor MWAIT
+ $EN_DIS
**/
UINT8 CpuPmMonitorMWait;
-/** Offset 0x0047 - Processor C6
- Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
- 0: Disabled, 1: Enabled
+/** Processor TurboMode Function
+ Enable(Default) or Disable Processor TurboMode Function
+ $EN_DIS
**/
- UINT8 CpuPmC6Enable;
+ UINT8 CpuPmTurboMode;
-/** Offset 0x0048 - Hardware P-States
- Hardware P-States - 0: Disable: Hardware chooses a P-state based on OS Request
- (Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
- 2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
- Mode with No Legacy Support.
- 0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
+/** Hardware P-States
+ Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
+ Native Mode:Hardware chooses a P-state based on OS guidance\n
+ Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
+ 0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
**/
UINT8 CpuPmProcessorHWPMEnable;
-/** Offset 0x0049 - Power Performance Tuning
- Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
- EPB, 2: PECI Controls EPB.
- 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
-**/
- UINT8 CpuPmPwrPerfTuning;
-
-/** Offset 0x004A - Configure SST-BF
- Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
- does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
-**/
- UINT8 CpuPmProcessorConfigurePbf;
-
-/** Offset 0x004B - CF9 Global Reset Promotion
- CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
- promoting CF9 reset to global(Default)</b>.
- 0: Disabled, 1: Enabled
-**/
- UINT8 MeGrPromotionEnabled;
-
-/** Offset 0x004C - Global Reset Lock
- Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
- 0: Disable locking the joint ME and host reset capability.
- 0: Disabled, 1: Enabled
-**/
- UINT8 MeGrLockEnabled;
-
-/** Offset 0x004D - Delayed Authentication Mode
- Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** HardwarePM Interrupt
+ Enable or Disable (Default) Hardware PM Interrupt
+ $EN_DIS
**/
- UINT8 DelayedAuthenticationMode;
+ UINT8 CpuPmProcessorHWPMInterrupt;
-/** Offset 0x004E - Delayed Authentication Mode Override
- Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+/** EPP Profile
+ Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
+ Power, 255: Power
+ 0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
**/
- UINT8 DelayedAuthenticationModeOverride;
+ UINT8 CpuPmProcessorEPPProfile;
-/** Offset 0x004F - Core Bios Done Message
- Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Boot Performance Mode
+ Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
+ 1: Max Efficiency
+ 0: Max Performance (Default), 1: Max Efficiency
**/
- UINT8 CoreBiosDoneEnabled;
+ UINT8 CpuPmBootPstate;
-/** Offset 0x0050 - End Of Post Message
- Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
- <b>2: Send in DXE(Default)</b>.
- 0:Disable, 1:Send in PEI, 2:Send in DXE
+/** Power Performance Tuning
+ Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
+ 2: PECI Controls EPB
+ 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
**/
- UINT8 EndOfPostMessage;
+ UINT8 CpuPmPwrPerfTuning;
-/** Offset 0x0051 - HMRFPO_LOCK Message
- Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor, 0: Disable, 1: Enable
+ $EN_DIS
**/
- UINT8 MeHmrfpoLockEnabled;
+ UINT8 ThermalMonitor;
-/** Offset 0x0052 - HMRFPO_ENABLE Message
- Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+/** FSPS Upd settings support
+ : FSPS Upd settings support
+ $EN_DIS
**/
- UINT8 MeHmrfpoEnableEnabled;
+ UINT8 FspsUpdSupport;
-/** Offset 0x0053
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
**/
- UINT8 UnusedUpdSpace1[1];
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
-/** Offset 0x0054
+/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
+
} FSPS_CONFIG;
-/** Fsp S UPD Configuration
-**/
+
typedef struct {
-/** Offset 0x0000
+/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-/** Offset 0x0020
+/** N/A
**/
- FSPS_CONFIG FspsConfig;
+ FSPS_ARCH2_UPD FspsArchUpd;
-/** Offset 0x0064
+/** N/A
**/
- UINT8 UnusedUpdSpace2[2];
+ FSPS_CONFIG FspsConfig;
-/** Offset 0x0066
+/** N/A
**/
UINT16 UpdTerminator;
+
} FSPS_UPD;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h
index 77ed502735..2e7cfa164c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -38,19 +38,19 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
typedef struct {
-
+
/** N/A
**/
UINT64 MicrocodeRegionBase;
-
+
/** N/A
**/
UINT64 MicrocodeRegionLength;
-
+
/** N/A
**/
UINT64 CodeRegionBase;
-
+
/** N/A
**/
UINT64 CodeRegionLength;
@@ -60,13 +60,11 @@ typedef struct {
typedef struct {
-/** Offset 0x0040 - Disable Port80 output in FSP-T
- Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
- 2:Disable Port80 Output, refer to FSP Integration Guide for details.
+/** Disable Port80 output in FSP-T
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
**/
UINT8 FsptPort80RouteDisable;
-
+
/** N/A
**/
UINT8 ReservedTempRamInitUpd[31];
@@ -75,23 +73,23 @@ typedef struct {
typedef struct {
-
+
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
/** N/A
**/
FSPT_ARCH2_UPD FsptArchUpd;
-
+
/** N/A
**/
FSPT_CORE_UPD FsptCoreUpd;
-
+
/** N/A
**/
FSPT_CONFIG FsptConfig;
-
+
/** N/A
**/
UINT16 UpdTerminator;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
index f71bc04561..27633c7462 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,35 +26,90 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _IIO_PCIE_CONFIG_UPD_H_
#define _IIO_PCIE_CONFIG_UPD_H_
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_LOGIC_IIO_STACK
-#define MAX_LOGIC_IIO_STACK 14
+#define MAX_LOGIC_IIO_STACK 18
#endif
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET 57
+/**
+ * Maximum number of IIO ports per IIO stack.
+ */
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK 8
#endif
-#ifndef MAX_IOU_PER_SOCKET
-#define MAX_IOU_PER_SOCKET 7
-#endif
+#define MAX_IIO_STACK 16
+#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
+#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
-#ifndef MAX_IIO_PORTS_PER_STACK
-#define MAX_IIO_PORTS_PER_STACK 1
+#if MAX_SOCKET <= 4
+
+//
+// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
+// However, we share R1S image with 4 socket SP image, no separate build for R1S.
+// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
+//
+#define MAX_IIO_PCIE_PER_SOCKET 10
+#else
+#define MAX_IIO_PCIE_PER_SOCKET 6
#endif
+#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
+
+#define IIO_BIFURCATE_xxxxxxxx 0xFE
+#define IIO_BIFURCATE_x4x4x4x4 0x0
+#define IIO_BIFURCATE_x4x4xxx8 0x1
+#define IIO_BIFURCATE_xxx8x4x4 0x2
+#define IIO_BIFURCATE_xxx8xxx8 0x3
+#define IIO_BIFURCATE_xxxxxx16 0x4
+#define IIO_BIFURCATE_x2x2x4x8 0x5
+#define IIO_BIFURCATE_x4x2x2x8 0x6
+#define IIO_BIFURCATE_x8x2x2x4 0x7
+#define IIO_BIFURCATE_x8x4x2x2 0x8
+#define IIO_BIFURCATE_x2x2x4x4x4 0x9
+#define IIO_BIFURCATE_x4x2x2x4x4 0xA
+#define IIO_BIFURCATE_x4x4x2x2x4 0xB
+#define IIO_BIFURCATE_x4x4x4x2x2 0xC
+#define IIO_BIFURCATE_x2x2x2x2x8 0xD
+#define IIO_BIFURCATE_x8x2x2x2x2 0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
+
+#define IIO_BIFURCATE_xxxxxxx4 0x40
+#define IIO_BIFURCATE_xxx2xxx2 0x41
+#define IIO_BIFURCATE_x1x1xxx2 0x42
+#define IIO_BIFURCATE_xxx2x1x1 0x43
+#define IIO_BIFURCATE_x1x1x1x1 0x44
+
+#define IIO_BIFURCATE_AUTO 0xFF
-#define MAX_IIO_PCIE_PER_SOCKET 1
+#define C1_UID 2
+#define C2_UID 3
-#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD
+/**
+ * VTBAR - Virtualization Technology BAR region size and alignment.
+ */
+#define IIO_VTBAR_LSB 16 // 64 kB
+#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
#pragma pack(1)
@@ -73,91 +128,6 @@ typedef enum {
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
-typedef struct {
- UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
- UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
- UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
- UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
- UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
- UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
- UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
- UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
- UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
- UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
- BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
- UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
- UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
- UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
- UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
-
- UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
- UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu
- UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
- UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
- UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
- UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
- UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
- UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
- UINT8 PcieGlobalAspm;
- UINT8 PcieMaxReadRequestSize;
-} UPD_IIO_PCIE_PORT_CONFIG;
-
-typedef struct {
- UINT8 Address;
- UINT8 Port;
- UINT8 MuxAddress;
- UINT8 MuxChannel;
-} IIO_VPP_CFG;
-
-typedef struct {
- UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
- UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
- UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
- UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
- UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
- UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
-
- UINT8 Reserved : 2;
-} IIO_SLOT_CFG;
-
-typedef struct {
- UINT8 Address; // SMBUS address of IO expander which provides NPEM
- UINT8 Bank; // Port or bank on IoExpander which provides NPEM
- UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
- UINT8 MuxChannel; // Channel of the MUX used to access NPEM
-} IIO_NPEM_CFG;
-
-typedef struct {
-
- IIO_VPP_CFG Vpp;
- IIO_NPEM_CFG Npem;
- IIO_SLOT_CFG Slot;
-
- UINT8 VppEnabled :1;
- UINT8 VppExpType :1;
- UINT8 NpemSupported :1;
-
- UINT8 SlotImplemented :1;
- UINT8 Retimer1Present :1;
- UINT8 Retimer2Present :1;
- UINT8 CommonClock :1;
- UINT8 SRIS :1;
-
- UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
- UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
- UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
- UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
-
- UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
-} IIO_BOARD_SETTINGS_PER_PORT;
-
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
@@ -182,7 +152,6 @@ typedef struct {
} PCI_BASE_LIMITS;
typedef struct {
- PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
@@ -211,37 +180,62 @@ typedef struct {
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
-#define IIO_BIFURCATE_xxxxxxxx 0xFE
-#define IIO_BIFURCATE_x4x4x4x4 0x0
-#define IIO_BIFURCATE_x4x4xxx8 0x1
-#define IIO_BIFURCATE_xxx8x4x4 0x2
-#define IIO_BIFURCATE_xxx8xxx8 0x3
-#define IIO_BIFURCATE_xxxxxx16 0x4
-#define IIO_BIFURCATE_x2x2x4x8 0x5
-#define IIO_BIFURCATE_x4x2x2x8 0x6
-#define IIO_BIFURCATE_x8x2x2x4 0x7
-#define IIO_BIFURCATE_x8x4x2x2 0x8
-#define IIO_BIFURCATE_x2x2x4x4x4 0x9
-#define IIO_BIFURCATE_x4x2x2x4x4 0xA
-#define IIO_BIFURCATE_x4x4x2x2x4 0xB
-#define IIO_BIFURCATE_x4x4x4x2x2 0xC
-#define IIO_BIFURCATE_x2x2x2x2x8 0xD
-#define IIO_BIFURCATE_x8x2x2x2x2 0xE
-#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
-#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
-#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
-#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
-#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
-#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
-#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
-#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
-#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
-#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
-#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
-#define IIO_BIFURCATE_AUTO 0xFF
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides VPP register
+ UINT8 Port; // Port or bank on IoExpander which provides VPP register
+ UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
+ UINT8 MuxChannel; // Channel of the MUX used to access VPP
+} IIO_VPP_CFG;
-#define C1_UID 2
-#define C2_UID 3
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides NPEM
+ UINT8 Bank; // Port or bank on IoExpander which provides NPEM
+ UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
+ UINT8 MuxChannel; // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
+ UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+ UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+ UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+ UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+ UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
+ UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+
+ UINT8 Reserved : 2;
+} IIO_SLOT_CFG;
+
+typedef struct {
+ //
+ // Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
+ //
+ IIO_VPP_CFG Vpp;
+ IIO_NPEM_CFG Npem;
+ IIO_SLOT_CFG Slot;
+
+ UINT8 VppEnabled :1; // If VPP is supported on given port
+ UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
+ UINT8 NpemSupported :1; // If NPEM is supported on given port
+
+ //
+ // Below is an excerpt IIO_PCIE_PORT_CONFIG
+ //
+ UINT8 SlotImplemented :1;
+ UINT8 Retimer1Present :1;
+ UINT8 Retimer2Present :1;
+ UINT8 CommonClock :1;
+ UINT8 SRIS :1;
+
+ //
+ // Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
+ //
+ UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
+ UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
+ UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
+ UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
+
+ UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
+} IIO_BOARD_SETTINGS_PER_PORT;
typedef enum {
IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
@@ -271,6 +265,13 @@ typedef enum {
IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
+
+ IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
+ IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
+ IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
+ IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
+ IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
+
IioBifurcation_Auto = IIO_BIFURCATE_AUTO
} IIO_BIFURCATION;
@@ -286,6 +287,9 @@ typedef struct {
IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
} IIO_BOARD_SETTINGS_PER_SOCKET;
+//
+// HOB to store board settings data created based on UBA data
+//
typedef struct {
IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
} IIO_BOARD_SETTINGS_HOB;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
index 6b4fa356d8..3921e38f56 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,108 +26,69 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
-**/
+ This file is automatically generated. Please do NOT modify !!!
+**/
#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#define _IIO_UNIVERSAL_DATA_HOB_H_
-#define DINO_UID 0
-#define PC_UID 1
-#define UB_UID 4
-#define CPM0_UID 5
-#define HQM0_UID 6
-
-#define IIO_UNIVERSAL_DATA_GUID { \
- 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
- 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
-}
+#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#if (MAX_SOCKET == 1)
- #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
+ #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#else
- #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
+ #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#endif //(MAX_SOCKET == 1)
-#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
-#endif
-
-#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
-#endif
-
-#ifndef MAX_CH
-#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
-#endif
-
-#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
-
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET 57
-#endif
-
-#ifndef MAX_IIO_PORTS_PER_STACK
-#define MAX_IIO_PORTS_PER_STACK 8
-#endif
-
+#define MAX_LOGIC_IIO_STACK 18
#ifndef MAX_IIO_PCIROOTS_PER_STACK
-#define MAX_IIO_PCIROOTS_PER_STACK 1
-#endif
-
-#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK 12
+#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
#endif
-#define MAX_LOGIC_IIO_STACK 14
-
-#define MAX_COMPUTE_DIE 1
-#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
-
-#pragma pack(1)
-
-typedef struct _UINT64_STRUCT {
- UINT32 lo;
- UINT32 hi;
-} UINT64_STRUCT, *PUINT64_STRUCT;
+#define MAX_COMPUTE_DIE 3
+#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
-typedef enum {
- TYPE_SCF_BAR = 0,
- TYPE_PCU_BAR,
- TYPE_MEM_BAR0,
- TYPE_MEM_BAR1,
- TYPE_MEM_BAR2,
- TYPE_MEM_BAR3,
- TYPE_MEM_BAR4,
- TYPE_MEM_BAR5,
- TYPE_MEM_BAR6,
- TYPE_MEM_BAR7,
- TYPE_SBREG_BAR,
- TYPE_MAX_MMIO_BAR
-} MMIO_BARS;
+#ifndef MAX_MESSAGE_LENGTH
+#define MAX_MESSAGE_LENGTH 500
#endif
-typedef struct {
- UINT8 Device;
- UINT8 Function;
-} IIO_PORT_INFO;
+#define DINO_UID 0
+#define PC_UID 1
+#define UB_UID 4
+#define CPM0_UID 5
+#define HQM0_UID 6
-typedef struct {
- UINT8 Major;
- UINT8 Minor;
- UINT8 Revision;
- UINT16 BuildNumber;
-} RC_VERSION;
+typedef enum {
+ IioStack0 = 0,
+ IioStack1 = 1,
+ IioStack2 = 2,
+ IioStack3 = 3,
+ IioStack4 = 4,
+ IioStack5 = 5,
+ IioStack6 = 6,
+ IioStack7 = 7,
+ IioStack8 = 8,
+ IioStack9 = 9,
+ IioStack10 = 10,
+ IioStack11 = 11,
+ IioStack12 = 12,
+ IioStack13 = 13,
+ IioStack14 = 14,
+ IioStack15 = 15,
+ IioStack16 = 16,
+ IioStackUnknown = 0xFF
+} IIO_STACK;
//--------------------------------------------------------------------------------------//
// Structure definitions for Universal Data Store (UDS)
//--------------------------------------------------------------------------------------//
+#pragma pack(1)
+
typedef struct {
UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
UINT8 PeerSocId; // Socket ID
@@ -137,52 +98,16 @@ typedef struct {
typedef struct {
UINT8 Valid;
- UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
UINT8 PcieSegment;
- UINT64_STRUCT SegMmcfgBase;
+ UINT64 SegMmcfgBase;
UINT32 StackPresentBitmap;
- UINT16 CxlPresentBitmap;
- UINT16 Cxl20CapableBitmap;
- UINT8 TotM3Kti;
+ UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
+ UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
UINT8 TotCha;
- UINT32 ChaList[MAX_CHA_MAP];
UINT32 SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;
-typedef struct {
- UINT8 Valid;
- UINT8 SocId;
- QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
-} QPI_IIO_DATA;
-
-typedef struct {
- IIO_PORT_INFO PortInfo[MAX_IIO_PORTS_PER_SOCKET];
-} IIO_DMI_PCIE_INFO;
-
-typedef struct _STACK_RES {
- UINT8 Personality;
- UINT8 BusBase; // Base of Bus configured for this stack
- UINT8 BusLimit; // Limit of Bus configured for this stack
- UINT16 IoBase; // Base of IO configured for this stack
- UINT16 IoLimit; // Limit of IO configured for this stack
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
- UINT8 PciResourceBusBase; // Base of Bus resource available for PCI devices
- UINT8 PciResourceBusLimit; // Limit of Bus resource available for PCI devices
- UINT16 PciResourceIoBase; // Base of IO resource available for PCI devices
- UINT16 PciResourceIoLimit; // Limit of IO resource available for PCI devices
- UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
- UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
- UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
- UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
- UINT32 VtdBarAddress; // NOTE: Obsolete, not used in next gen platforms
-} STACK_RES;
-
/**
* PCI resources that establish one PCI hierarchy for PCI Enumerator.
*/
@@ -198,122 +123,87 @@ typedef struct {
UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
} UDS_PCIROOT_RES;
+/**
+ * This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
+ * One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
+ */
typedef struct {
UINT8 Personality;
UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
+ UINT8 Segment; // Segment for this stack
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
+ UINT8 Reserved[3]; // Reserved for alignment
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
- UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
UINT64 VtbarAddress; // VT-d Base Address
- UINT64 ChbcrBarAddress;
+ UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
+ UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
} UDS_STACK_RES;
+/**
+ * This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
+ // the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
+ */
typedef struct {
UINT8 Valid;
- UINT8 SocketID; // Socket ID of the IIO (0..3)
- UINT8 BusBase;
- UINT8 BusLimit;
+ UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT16 IoBase;
UINT16 IoLimit;
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
+ UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
} UDS_SOCKET_RES;
+/**
+ * This structore keeps resource ranges configured in whole system.
+ */
typedef struct {
- UINT8 Valid;
- UINT8 SocketID; // Socket ID of the IIO (0..3)
- UINT8 BusBase;
- UINT8 BusLimit;
- UINT16 PciResourceIoBase;
- UINT16 PciResourceIoLimit;
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
- UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
- IIO_DMI_PCIE_INFO PcieInfo; // NOTE: Obsolete, not used in next gen platforms
-} IIO_RESOURCE_INSTANCE;
+ UINT16 SystemIoBase; // System IO Base
+ UINT16 SystemIoLimit; // System IO Limit
+ UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
+ UINT32 SystemIoApicLimit;
+ UINT32 SystemMmio32Base; // System low MMIO base
+ UINT32 SystemMmio32Limit; // System low MMIO limit
+ UINT64 SystemMmio64Base; // System high MMIO Base
+ UINT64 SystemMmio64Limit; // System high MMIO Limit
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ UINT64 PciExpressBase; // PCI Config Space base address
+ UINT64 PciExpressSize; // PCI Config Space size
+ UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
+ UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ UINT16 IoGranularity;
+ UINT32 Mmio32Granularity;
+ UINT64 Mmio64Granularity;
+ UINT32 UboxMmioSize;
+ UINT32 MemTolm;
+ UINT32 MemTsegSize;
+ UINT32 MaxAddressBits;
+} PLATFORM_DATA;
typedef struct {
- UINT16 PlatGlobalIoBase; // Global IO Base
- UINT16 PlatGlobalIoLimit; // Global IO Limit
- UINT32 PlatGlobalMmio32Base; // Global Mmiol base
- UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
- UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
- UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
- QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
- QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
- UINT16 SystemIoBase; // System IO Base
- UINT16 SystemIoLimit; // System IO Limit
- UINT32 SystemMmio32Base; // System low MMIO base
- UINT32 SystemMmio32Limit;
- UINT32 Mmio32Granularity;
- UINT64 SystemMmio64Base; // System high MMIO Base
- UINT64 SystemMmio64Limit; // System high MMIO Limit
- UINT64 Mmio64Granularity;
- UINT32 MemTsegSize;
- UINT64 PciExpressBase;
- UINT32 PciExpressSize;
- UINT32 MemTolm;
- UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
- UINT8 numofIIO;
- UINT8 MaxBusNumber;
- UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
- UINT8 EVMode;
- UINT8 SkuPersonality[MAX_SOCKET];
- UINT16 IoGranularity;
- UINT32 MmiolGranularity;
- UINT64_STRUCT MmiohGranularity;
- UINT8 RemoteRequestThreshold; //5370389
- UINT32 UboxMmioSize;
- UINT32 MaxAddressBits;
-} PLATFORM_DATA;
+ BOOLEAN FailFlag;
+ CHAR16 Message[MAX_MESSAGE_LENGTH];
+} REBALANCE_FAIL_INFO;
typedef struct {
- UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
+ UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
- UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
- UINT8 IsocEnable;
- UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
- UINT8 DmiVc1;
- UINT8 DmiVcm;
- UINT32 CpuPCPSInfo;
- UINT8 cpuSubType;
+ UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 SystemRasType;
- UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
- UINT16 tolmLimit;
- RC_VERSION RcVersion;
- BOOLEAN MsrTraceEnable;
- UINT8 DdrXoverMode; // DDR 2.2 Mode
- // For RAS
- UINT8 bootMode;
- UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
+ UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT8 OutSncEn;
UINT8 OutNumOfCluster;
- UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
- UINT16 LlcSizeReg;
- UINT8 chEnabled[MAX_SOCKET][MAX_CH];
- UINT8 memNode[MC_MAX_NODE];
- UINT8 IoDcMode;
- UINT8 DfxRstCplBitsEn;
UINT8 BitsUsed; //For 5 Level Paging
+ REBALANCE_FAIL_INFO RebalanceFailInfo;
} SYSTEM_STATUS;
typedef struct {
@@ -322,32 +212,7 @@ typedef struct {
UINT32 OemValue;
} IIO_UDS;
-typedef enum {
- //for ICX
- IioStack0 = 0, // DmiAsPcie
- IioStack1 = 1, // IOU0
- IioStack2 = 2, // IOU1
- IioStack3 = 3, // IOU2
- IioStack4 = 4, // IOU3
- IioStack5 = 5, // IOU4
- //for SPR
- IioStack6 = 6, // IOU5
- IioStack7 = 7,
- IioStack8 = 8,
- IioStack9 = 9,
- IioStack10 = 10,
- IioStack11 = 11,
- //for later SOC
- IioStack12 = 12,
- IioStack13 = 13,
- IioStack14 = 14,
- IioStack15 = 15,
- IioStack16 = 16,
- IioStack17 = 17,
- IioStack18 = 18,
- IioStackUnknown = 0xFF
-} IIO_STACK;
-
#pragma pack()
-#endif //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
+#endif // _IIO_UNIVERSAL_DATA_HOB_H_
+
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
index ad3eec3b3d..9300793103 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _MEMORY_MAP_DATA_HOB_H_
@@ -34,37 +36,51 @@ are permitted provided that the following conditions are met:
#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
+#define MAX_IMC 12 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
-#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGES
+#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
#endif
-#define MAX_CXL_AMT 0
+#ifndef MAX_CXL_HOST_BRIDGE_WAYS
+#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
+#endif
+
+//
+// Macro definitions for abstracted memory decoding target. The data structure is designed to
+// iterate iMC and CXL host bridge host decoded memory in an unified way.
+// definition for GNRSRF/GNRD/GRR
+//
+#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
+
#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
-#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#endif
#ifndef MAX_SPARE_RANK
-#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
+#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#endif
#ifndef MAX_HBM_IO
-#define MAX_HBM_IO 4
+#define MAX_HBM_IO 4
#endif
#ifndef MAX_DIMM
-#define MAX_DIMM 2 // Max DIMM per channel
+#define MAX_DIMM 2 // Max DIMM per channel
#endif
#ifndef MAX_RANK_DIMM
@@ -72,7 +88,7 @@ are permitted provided that the following conditions are met:
#endif
#ifndef MAX_DRAM_CLUSTERS
-#define MAX_DRAM_CLUSTERS 4
+#define MAX_DRAM_CLUSTERS 6
#endif
#ifndef MAX_SAD_RULES
@@ -83,17 +99,17 @@ are permitted provided that the following conditions are met:
#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
#endif
-#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
+#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
-#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
-#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
+#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
+#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
// NGN
-#define NGN_MAX_SERIALNUMBER_STRLEN 4
-#define NGN_MAX_PARTNUMBER_STRLEN 30
-#define NGN_FW_VER_LEN 4
-#define NGN_LOG_TYPE_NUM 2
-#define NGN_LOG_LEVEL_NUM 2
+#define NGN_MAX_SERIALNUMBER_STRLEN 4
+#define NGN_MAX_PARTNUMBER_STRLEN 30
+#define NGN_FW_VER_LEN 4
+#define NGN_LOG_TYPE_NUM 2
+#define NGN_LOG_LEVEL_NUM 2
/**
* Memory channel index conversion macros.
@@ -115,25 +131,14 @@ are permitted provided that the following conditions are met:
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
-typedef UINT8 CXL_INTLV_SET_KEY;
+typedef UINT8 INTLV_SET_KEY;
-#define FSP_RESERVED1_LEN 77
-#define FSP_RESERVED2_LEN 2174
-#define FSP_RESERVED3_LEN 21
-#define FSP_RESERVED4_LEN 130
-#define FSP_RESERVED5_LEN 10
-#define FSP_RESERVED6_LEN 800
+#define FSP_RESERVED1_LEN 5748
+#define FSP_RESERVED2_LEN 1
+#define FSP_RESERVED3_LEN 220
+#define FSP_RESERVED4_LEN 10
#pragma pack(1)
-typedef enum {
- DIMM_RANK_MAP_OUT_UNKNOWN = 0,
- DIMM_RANK_MAP_OUT_MEM_DECODE,
- DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
- DIMM_RANK_MAP_OUT_RANK_DISABLED,
- DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
- DIMM_RANK_MAP_OUT_MAX
-} DIMM_RANK_MAP_OUT_REASON;
-
struct RankDevice {
UINT8 enabled; // 0 = disabled, 1 = enabled
UINT8 logicalRank; // Logical Rank number (0 - 7)
@@ -154,55 +159,58 @@ typedef struct firmwareRev {
} FIRMWARE_REV;
typedef struct DimmDevice {
- UINT8 Present;
- BOOLEAN Enabled;
- UINT8 DcpmmPresent; // 1 - This is a DCPMM
- UINT8 X4Present;
- UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
- UINT8 NumRanks;
- UINT8 keyByte;
- UINT8 actKeyByte2; // Actual module type reported by SPD
- UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
- UINT8 dimmTs; // Thermal sensor data.
- UINT16 VolCap; // Volatile capacity (AEP DIMM only)
- UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
- UINT16 DimmSize;
- UINT32 NVmemSize;
- UINT16 SPDMMfgId; // Module Mfg Id from SPD
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
- struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
- UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
- UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
- UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
- struct firmwareRev FirmwareVersion; // Firmware revision
- struct RankDevice rankList[MAX_RANK_DIMM];
- UINT16 InterfaceFormatCode;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT16 FisVersion; // Firmware Interface Specification version
- UINT8 DimmSku; // Dimm SKU info
- UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
- UINT16 manufacturingDate; // Date the NVDIMM was manufactured
- INT32 commonTck;
- UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
- BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
- UINT8 CidBitMap; // SubRankPer CS for DIMM device
- UINT16 SPDRegVen; // Register Vendor ID in SPD
- DIMM_RANK_MAP_OUT_REASON MapOutReason;
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DcpmmPresent; // 1 - This is a DCPMM
+ UINT8 X4Present;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MCR NumRanks and NumPackageRanks may differ
+ UINT8 keyByte;
+ UINT8 actKeyByte2; // Actual module type reported by SPD
+ UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
+ UINT8 dimmTs; // Thermal sensor data.
+ UINT16 VolCap; // Volatile capacity (AEP DIMM only)
+ UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
+ UINT16 DimmSize;
+ UINT16 SPDMMfgId; // Module Mfg Id from SPD
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
+ struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
+ UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
+ struct firmwareRev FirmwareVersion; // Firmware revision
+ struct RankDevice rankList[MAX_RANK_DIMM];
+ UINT16 InterfaceFormatCode;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ UINT8 DimmSku; // Dimm SKU info
+ UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
+ UINT16 manufacturingDate; // Date the NVDIMM was manufactured
+ INT32 commonTck;
+ UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+ BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
+ UINT8 CidBitMap; // SubRankPer CS for DIMM device
+ UINT16 SPDRegVen; // Register Vendor ID in SPD
+ UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
+ BOOLEAN DimmChanged;
} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
-struct ChannelDevice {
+typedef struct ChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 NumRanks; // Number of ranks on this channel
UINT8 chFailed;
UINT8 ngnChFailed;
- UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
@@ -210,11 +218,11 @@ struct ChannelDevice {
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
-};
+} CHANNEL_DEVICE;
-struct memcontroller {
+typedef struct memcontroller {
UINT32 MemSize;
-};
+} MEMCONTROLLER;
typedef enum {
MemTypeNone = 0,
@@ -251,8 +259,8 @@ typedef struct SADTable {
UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
- UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
- UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
+ UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
+ UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
BOOLEAN local; // 0 - Remote 1- Local
UINT8 IotEnabled; // To indicate if IOT is enabled
UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
@@ -260,8 +268,9 @@ typedef struct SADTable {
UINT8 tgtGranularity; // Interleave mode for target list
UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
UINT8 HostBridgeGran; // Host bridge interleaving granularity.
+ UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges.
UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
- CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
+ INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
} SAD_TABLE;
typedef struct socket {
@@ -271,10 +280,9 @@ typedef struct socket {
UINT8 imcEnabled[MAX_IMC];
UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
- UINT32 SktMemSize2LM; // Total memory excluded from Limit
SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
- struct memcontroller imc[MAX_IMC];
- struct ChannelDevice ChannelInfo[MAX_CH];
+ MEMCONTROLLER imc[MAX_IMC];
+ CHANNEL_DEVICE ChannelInfo[MAX_CH];
} MEMMAP_SOCKET;
typedef struct {
@@ -287,9 +295,10 @@ typedef struct SystemMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
- UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory
- UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
+ UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} SYSTEM_MEMORY_MAP_ELEMENT;
@@ -300,8 +309,6 @@ typedef struct SystemMemoryMapHob {
// All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
//
UINT8 TotalClusters;
-
- UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
@@ -310,14 +317,9 @@ typedef struct SystemMemoryMapHob {
UINT16 memFreq; // Mem Frequency
UINT16 HbmFreq; // HBM Frequency in MHz.
UINT8 memMode; // 0 - Independent, 1 - Lockstep
- UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
- UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage;
- BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS
- BOOLEAN EkvPresent; // Set if EKV controller on system
- BOOLEAN BwvPresent; // Set if BWV controller on system
- BOOLEAN CwvPresent; // Set if CWV controller on system
UINT8 XMPProfilesSup;
UINT8 XMPCapability;
//
@@ -336,35 +338,20 @@ typedef struct SystemMemoryMapHob {
UINT8 NumChPerMC;
UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
- UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup;
- UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar;
+ UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
+ UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
MEMMAP_SOCKET Socket[MAX_SOCKET];
- UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
-
- UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo;
- UINT8 LatchSystemShutdownState;
- BOOLEAN IsWpqFlushSupported;
- UINT8 EadrSupport;
- UINT8 EadrCacheFlushMode;
- UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
- UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
+ UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
+
+ UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
- BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
- UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
- UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
- UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
- UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
- UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
- UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
- UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
- UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
- UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
+ UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
- UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
+ UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
+ BOOLEAN McrMemFreqRangeEn; // MCR Memory Frequency range enabled.
} SYSTEM_MEMORY_MAP_HOB;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h
index f1d55542c3..6eeabd3e1b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,13 +26,14 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
#define _PREV_BOOT_ERR_SRC_HOB_H_
-#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
-{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h
index b6d88f5c30..6890066478 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,42 +26,41 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _SYSTEM_INFO_HOB_H_
#define _SYSTEM_INFO_HOB_H_
-#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
+#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK 12
+#define MAX_IIO_STACK 16
#endif
-#define MAX_LOGIC_IIO_STACK 14
+#define MAX_LOGIC_IIO_STACK 18
+#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
+#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
+#define MAX_IMC 12 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
-#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
-#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
-
#pragma pack(1)
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
@@ -76,7 +75,6 @@ typedef enum {
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
-#endif
typedef enum {
ReservedMemSs,
@@ -95,7 +93,7 @@ typedef enum BootMode {
// in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
// init and be optimized for speed.
-} BootMode;
+} BOOT_MODE;
//
// This is used to determine what type of die is connected to a UPI link
@@ -163,19 +161,6 @@ typedef struct {
} HPM_VSEC_RESOURCE;
-//
-// Stack id swap information, which includes stack swap flag and the new stack id swap array.
-//
-typedef struct {
- BOOLEAN StackSwapFlag;
- UINT8 StackIdSwapArray[MAX_IIO_STACK];
-} STACKID_SWAP_INFO;
-
-typedef struct {
- UINT64 Cxl1p1RcrbBase;
- BOOLEAN Cxl1p1RcrbValid;
-} CXL_1P1_RCRB;
-
typedef struct {
UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
@@ -188,7 +173,6 @@ typedef struct {
UINT8 segmentSocket[MAX_SOCKET];
UINT8 KtiPortCnt;
UINT32 socketPresentBitMap;
- UINT32 SecondaryNodeBitMap;
UINT32 FpgaPresentBitMap;
UINT32 mmCfgBase;
UINT64 SocketMmCfgBase[MAX_SOCKET];
@@ -220,13 +204,17 @@ typedef struct {
BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
BOOLEAN HbmSku;
- UINT8 HcxType[MAX_SOCKET];
- STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
- CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
UINT8 ChopType; //Compute Die Chop Type
UINT8 MdfInstCount;
+ UINT32 UboxMmioSize;
+ UINT32 UboxScfMmioSize;
+ UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
+ UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
+ UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
} CPU_CSR_ACCESS_VAR;
typedef struct {
@@ -261,7 +249,7 @@ typedef struct {
UINT32 CheckPoint;
UINT8 ResetRequired;
UINT8 Emulation;
- BootMode SysBootMode;
+ BOOT_MODE SysBootMode;
CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
UINT64 CpuFreq;
UINT8 SocketId;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h
index 42b5cc20d5..5f6afc2146 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,25 +26,32 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _CXL_NODE_HOB_
#define _CXL_NODE_HOB_
-#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
#ifndef MAX_CXL_HDM_RANGES
#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
#endif
#ifndef MAX_CXL_PER_SOCKET
-#define MAX_CXL_PER_SOCKET 8
+#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
#endif
#define CXL_NODE_ATTR_MEM BIT0
#define CXL_NODE_ATTR_PERSISTENT BIT1
#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
#define CXL_NODE_ATTR_ACCELERATOR BIT3
+#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
typedef UINT32 CXL_NODE_ATTR;
@@ -75,6 +82,7 @@ typedef struct {
UINT32 Size;
UINT8 Ways;
UINT8 SocketBitmap;
+ BOOLEAN AcpiSratSpMemFlag;
CXL_EFI_MEM_TYPE EfiMemType;
CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
@@ -86,7 +94,7 @@ typedef struct {
//
// CXL node info for UEFI memory map and ACPI tables construction
//
- CXL_NODE_INFO CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
+ CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
} CXL_NODE_SOCKET;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h
deleted file mode 100644
index 7c54749304..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/** @file
-
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
-**/
-
-#ifndef _ENHANCED_WARNING_LOG_LIB_
-#define _ENHANCED_WARNING_LOG_LIB_
-
-#define FSP_RESERVED_LEN 12
-
-#pragma pack(1)
-
-///
-/// Enhanced Warning Log Header
-///
-typedef struct {
- EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
- UINT32 Size; /// Total size in bytes including the header and buffer
- UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
- /// of the buffer immediately following this structure
- /// Can be used to determine if buffer has sufficient space for next entry
- UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
- /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
- /// Consumers can ignore CRC check if not needed.
- UINT32 Reserved; /// Reserved for future use, must be initialized to 0
-} EWL_HEADER;
-
-///
-/// List of all entry types supported by this revision of EWL
-///
-typedef enum {
- EwlType0 = 0,
- EwlType1 = 1,
- EwlType2 = 2,
- EwlType3 = 3,
- EwlType4 = 4,
- EwlType5 = 5,
- EwlType6 = 6,
- EwlType7 = 7,
- EwlType8 = 8,
- EwlType9 = 9,
- EwlType10 = 10,
- EwlType11 = 11,
- EwlType12 = 12,
- EwlType13 = 13,
- EwlType14 = 14,
- EwlType15 = 15,
- EwlType16 = 16,
- EwlType17 = 17,
- EwlType18 = 18,
- EwlType19 = 19,
- EwlType20 = 20,
- EwlType21 = 21,
- EwlType22 = 22,
- EwlType23 = 23,
- EwlType24 = 24,
- EwlType25 = 25,
- EwlType26 = 26,
- EwlType27 = 27,
- EwlType28 = 28,
- EwlType29 = 29,
- EwlType30 = 30,
- EwlType31 = 31,
- EwlType32 = 32,
- EwlTypeMax,
- EwlTypeOem = 0x8000,
- EwlTypeDelim = MAX_INT32
-} EWL_TYPE;
-
-///
-/// EWL severities
-///
-typedef enum {
- EwlSeverityInfo,
- EwlSeverityWarning,
- EwlSeverityFatal,
- EwlSeverityMax,
- EwlSeverityDelim = MAX_INT32
-} EWL_SEVERITY;
-
-
-///
-/// Generic entry header for parsing the log
-///
-typedef struct {
- EWL_TYPE Type;
- UINT16 Size; /// Entries will be packed by byte in contiguous space
- EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
-} EWL_ENTRY_HEADER;
-
-///
-/// Legacy content provides context of the warning
-///
-typedef struct {
- UINT8 MajorCheckpoint; // EWL Spec - Appendix B
- UINT8 MinorCheckpoint;
- UINT8 MajorWarningCode; // EWL Spec - Appendix A
- UINT8 MinorWarningCode;
-} EWL_ENTRY_CONTEXT;
-
-///
-/// Legacy content to specify memory location
-///
-typedef struct {
- UINT8 Socket; /// 0xFF = n/a
- UINT8 Channel; /// 0xFF = n/a
- UINT8 PseudoChannel; /// 0xFF = n/a
- UINT8 Dimm; /// 0xFF = n/a
- UINT8 Rank; /// 0xFF = n/a
-} EWL_ENTRY_MEMORY_LOCATION;
-
-///
-/// Type 3 = Enhanced type for command, control IO errors
-///
-typedef struct {
- EWL_ENTRY_HEADER Header;
- EWL_ENTRY_CONTEXT Context;
- EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
- UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
- UINT8 EyeSize; // 0xFF = n/a
-} EWL_ENTRY_TYPE3;
-
-#pragma pack()
-
-///
-/// Enhanced Warning Log Spec defined data log structure
-///
-typedef struct {
- EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
- UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
-} EWL_PUBLIC_DATA;
-
-///
-/// EWL private data structure. This is going to be implementation dependent
-/// When we separate OEM hooks via a PPI, we can remove this
-///
-typedef struct {
- UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
- UINT32 numEntries; // Number of entries currently logged
- EWL_PUBLIC_DATA status; // Spec defined EWL
-} EWL_PRIVATE_DATA;
-
-
-#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h
deleted file mode 100644
index 5d09dd2d18..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/** @file
- Header file for Firmware Version Information
- @copyright
- Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
- UINT8 Count; ///< Offset 28 Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
index 6d5ba0a37b..7150e5ed8e 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,15 +26,28 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
-#ifndef _FSP_ACPI_HOBS_H_
-#define _FSP_ACPI_HOBS_H_
+#ifndef __FSP_ACPI_HOBS__
+#define __FSP_ACPI_HOBS__
+
+//Typecast HOB pointer to APEI table structure of ACPI version 6.2
+#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
//Typecast HOB pointer to ACPI CXL CEDT table structure
#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
+
+// Typecast HOB pointer to EWL_PRIVATE_DATA.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
+
//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
-#endif //#ifndef _FSP_ACPI_HOBS_H_
+#endif // __FSP_ACPI_HOBS__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h
deleted file mode 100644
index f99c3bc36b..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
- Intel FSP definition from Intel Firmware Support Package External
- Architecture Specification v2.2.
- @copyright
- Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _FSP_EAS_H_
-#define _FSP_EAS_H_
-
-#include <Uefi.h>
-#include <Guid/GuidHobFspEas.h>
-#include <Guid/FspHeaderFile.h>
-#include <FspEas/FspApi.h>
-
-#endif // _FSP_EAS_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
index af0dc5055e..ce694e9c91 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef __FSP_EDPC_PARAM__
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h
index ecc2d6fdf7..6b418c514c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,20 +26,23 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _FSP_ERROR_INFO_HOB_H_
#define _FSP_ERROR_INFO_HOB_H_
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-#include <Pi/PiStatusCode.h>
-
-#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
+///
+/// GUID value indicating the FSP error information.
+///
+#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
+#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
+///
+/// FSP Error Information Block.
+///
#pragma pack(1)
-
typedef struct {
///
/// GUID HOB header.
@@ -81,4 +84,4 @@ typedef struct {
#pragma pack()
-#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
+#endif //_FSP_ERROR_INFO_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h
new file mode 100644
index 0000000000..97e3710965
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h
@@ -0,0 +1,70 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
+#define _FSP_EXT_MEMORY_PPR_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
+
+#pragma pack(1)
+
+typedef struct FspExtPprAddr {
+ UINT8 Status;
+ UINT8 ErrorType;
+ UINT8 Socket;
+ UINT8 MemoryController;
+ UINT8 Channel;
+ UINT8 Dimm;
+ UINT8 Bank;
+ UINT32 Row;
+ UINT8 Rank;
+} FSP_EXT_PPR_ADDR;
+
+typedef struct FspExtPprDdrInfo {
+ UINT8 Count;
+ FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
+} FSP_EXT_DDR_PPR_INFO;
+
+typedef struct FspExtMemoryPprData {
+ FSP_EXT_DDR_PPR_INFO DdrPprInfo;
+} FSP_EXT_MEMORY_PPR_DATA;
+
+typedef struct FspExtMemoryPprHob {
+ FSP_EXT_HEADER Header;
+ FSP_EXT_MEMORY_PPR_DATA Data;
+} FSP_EXT_MEMORY_PPR_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_MEMORY_PPR_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtSystemMemoryMapHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtSystemMemoryMapHob.h
new file mode 100644
index 0000000000..864d53ac45
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtSystemMemoryMapHob.h
@@ -0,0 +1,161 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
+
+#pragma pack(1)
+
+typedef struct FspDimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MCR NumRanks and NumPackageRanks may differ
+ UINT8 ActKeyByte2; // Actual module type reported by SPD
+ UINT16 DimmSize;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
+ UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ INT32 CommonTck;
+ UINT16 SpdRegVen; // Register Vendor ID in SPD
+ UINT8 DataWidth;
+} FSP_EXT_DIMM_DEVICE;
+
+typedef struct FspExtMemoryDimmDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
+} FSP_EXT_DIMM_DEVICE_INFO;
+
+typedef struct FspMemoryChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 ChFailed;
+ UINT8 NgnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
+} FSP_EXT_MEMORY_CHANNEL_DEVICE;
+
+typedef struct FspMemoryController {
+ UINT8 ImcEnabled;
+ UINT32 MemSize;
+} FSP_EXT_MEMORY_CONTROLLER;
+
+typedef struct FspExtMemoryChannelDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
+} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
+
+typedef struct FspExtMemoryControllerInfo {
+ UINT8 Count;
+ UINT8 NumChPerMC;
+ FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
+} FSP_EXT_MEMORY_CONTROLLER_INFO;
+
+typedef struct FspMemoryMapSocket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
+} FSP_EXT_MEMORY_MAP_SOCKET;
+
+typedef struct FspExtMemMapSocketInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
+} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
+
+typedef struct FspMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} FSP_EXT_MEMORY_MAP_ELEMENT;
+
+typedef struct FspExtMemMapElementInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
+} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
+
+typedef struct FspExtRasInfo {
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+} FSP_EXT_RAS_INFO;
+
+typedef struct FspExtMemoryConfigurationInfo {
+ UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT32 MemSize; // Total physical memory size
+ UINT16 MemFreq;
+ UINT8 MemMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage; // Mem Frequency
+ UINT8 ErrorCorrectionType;
+} FSP_EXT_MEMORY_CONFIGURATION_INFO;
+
+typedef struct FspExtSystemMemoryMapData {
+ FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
+ FSP_EXT_RAS_INFO RasInfo;
+ FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
+ FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
+} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
+
+typedef struct FspExtSystemMemoryMapDataHob{
+ FSP_EXT_HEADER Header;
+ FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
+} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h
new file mode 100644
index 0000000000..c8df3acaef
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h
@@ -0,0 +1,61 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_GLOBALS_
+#define _FSP_EXT_GLOBALS_
+
+#define FSP_MAX_SOCKET MAX_SOCKET
+#define FSP_MAX_IMC MAX_IMC
+#define FSP_MAX_MC_CH MAX_MC_CH
+#define FSP_MAX_DIMM MAX_DIMM
+#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
+#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
+#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
+#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
+
+typedef struct FspExtHeader {
+ UINT64 Magic;
+ UINT32 DataLength;
+ UINT32 CheckSum;
+} FSP_EXT_HEADER;
+
+#endif // _FSP_EXT_GLOBALS_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h
index d90f785578..cbee351279 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
-#define FSPT_UPD_SIGNATURE 0x545F445055525053 /* 'SPRUPD_T' */
+#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
-#define FSPM_UPD_SIGNATURE 0x4D5F445055525053 /* 'SPRUPD_M' */
+#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
-#define FSPS_UPD_SIGNATURE 0x535F445055525053 /* 'SPRUPD_S' */
+#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
index 5aa10ee72e..ba7767267f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -35,12 +35,26 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
-#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } };
-
#pragma pack(1)
typedef struct {
+/** RAS Log Level.
+ RAS Log setup options.
+ 0:None, 1:MIN (BASIC_FLOW), 2:MID (BASIC_FLOW, FUNC_FLOW), 3:MAX (BASIC_FLOW, FUNC_FLOW, REG)
+**/
+ UINT8 RasLogLevel;
+
+/** WHEA FV Base Address
+ The physical memory-mapped base address of the WHEA (FV).
+**/
+ UINT64 WheaFvBase;
+
+/** WHEA FV Base Size
+ The size of the WHEA FV region in bytes
+**/
+ UINT64 WheaFvBaseSize;
+
/** WHEA Support
Enable/Disable WHEA support.
0:Disable, 1:Enable
@@ -69,15 +83,216 @@ typedef struct {
**/
UINT8 PcieErrInjActionTable;
+/** SGX Memory Error Injection Support
+ Enable/Disable Error Injection Support in SGX Memory.
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 SgxErrorInjEn;
+
+/** Os Native AER Support
+ Select FFM or OS native for AER error handling. If select OS native, BIOS also initialize
+ FFM first until handshake, which depends on OS capability in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 OsNativeAerSupport;
+
+/** IIO MCA Support.
+ Enable/Disable IIO MCA Support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 IoMcaEn;
+
+/** System Errors
+ System Error Enable/Disable setup options.
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 SystemErrorEn;
+
+/** CPU CrashLog Feature
+ The feature helps collecting crash data from OOBMSM SSRAM
+ 0:Disabled, 1:Enabled,2:Auto
+**/
+ UINT8 CpuCrashLogFeature;
+
+/** MCERR Trigger CrashLog Disable
+ The feature helps to disable MCERR to trigger crash log
+ 0:No, 1:Yes
+**/
+ UINT8 McerrTriggerDisable;
+
+/** Smbus Error Recovery
+ Enable or Disable(Default) Smbus Error Recovery
+ 0:Disabled, 1:SMI, 2:Error Pin
+**/
+ UINT8 SmbusErrorRecovery;
+
+/** EMCA Error Support
+ Enable/Disable EMCA Error support
+ 0:Disable, 1:Enable
+**/
+ UINT8 EmcaEn;
+
+/** EMCA Logging Support
+ Enable/Disable EMCA Logging
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogEn;
+
+/** LMCE Support
+ Enable/Disable Local MCE firmware support
+ 0:Disable, 1:Enable
+**/
+ UINT8 LmceEn;
+
+/** EMCA MCE-SMI Enable
+ Enable/Disable EMCA Uncorrected SMI for gen2
+ 0:Disable, 2:EMCA gen2 MSMI
+**/
+ UINT8 EmcaMsmiEn;
+
+/** EMCA CMCI-SMI Morphing
+ Enable/Disable EMCA CSMI
+ 0:Disable, 2:EMCA gen2 CSMI
+**/
+ UINT8 EmcaCsmiEn;
+
+/** EMCA CMCI-SMI Threshold
+ Set the threshold of CSMI
+**/
+ UINT16 EmcaCsmiThreshold;
+
+/** CSMI Dynamic Disable
+ Enable/Disable CSMI when error threshold reached
+ 0:Disable, 1:Enable
+**/
+ UINT8 CsmiDynamicDisable;
+
+/** Ignore OS ELOG Opt-in
+ Enable/Disable Ignore OS ELOG Opt-in and log
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogIgnOptin;
+
+/** Corrected Error eLog
+ Enable/Disable Corrected Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogCorrErrEn;
+
+/** Memory Error eLog
+ Enable/Disable Memory Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogMemErrEn;
+
+/** Processor Error eLog
+ Enable/Disable Processor Error eLog
+ 0:Disable, 1:Enable
+**/
+ UINT8 ElogProcErrEn;
+
+/** Ubox Error Mask
+ Mask SMI generation for Ubox Error
+ 0:Disable, 1:Enable
+**/
+ UINT8 UboxErrorMask;
+
+/** Corrected Error Cloaking
+ Mask Corrected errors from OS/SW visibility only when EMCA is enabled
+ 0:Disable, 1:Enable
+**/
+ UINT8 CeCloakingEn;
+
+/** Memory Corrected Error
+ Enable/Disable Memory Corrected Error
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 CorrMemErrEn;
+
+/** Mca Bank Error Injection Support
+ Enable/Disable Mca Bank Error Injection Support.
+ $EN_DIS
+**/
+ UINT8 McaBankErrInjEn;
+
+/** Whea Log Memory Error
+ Enable/Disable Whea Log Memory Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogMemoryEn;
+
+/** Whea Log Processor Error
+ Enable/Disable Whea Log Processor Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogProcEn;
+
+/** Whea Log PCI Error
+ Enable/Disable Whea Log PCI Error
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 WheaLogPciEn;
+
+/** Viral Status
+ Enable/Disable Viral
+ $EN_DIS
+**/
+ UINT8 ViralEn;
+
+/** System Memory Poison
+ Enable/Disable System Memory Poison.
+ $EN_DIS
+**/
+ UINT8 DfxPoisonEn;
+
+/** Clear Shadow Registers
+ Enable/Disable clearing shadow registers.
+ $EN_DIS
+**/
+ UINT8 ClearShadowRegisters;
+
+/** PCIE Corrected Error Threshold Counter
+ Enable/Disable PCIE Corrected Error Counter.
+ $EN_DIS
+**/
+ UINT8 PcieCorErrCntr;
+
+/** PCIE Corrected Error Threshold Counter
+ 0x00000001 - 0x0000ffff.
+**/
+ UINT32 PcieCorErrThres;
+
/** IIO eDPC Support
Enable/Disable IIO eDPC Support.
0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
**/
UINT8 EdpcEn;
+/** IIO eDPC Interrupt
+ Enable/Disable IIO eDPC Interrupt.
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 EdpcInterrupt;
+
+/** IpmiIoBase
+ Address of IpmiIoBase
+**/
+ UINT16 IpmiIoBase;
+
+/** Trigger SW Error Threshold
+ Enable or Disable Sparing trigger SW Error Match Threshold.
+ 0:Disable, 1:Enable
+**/
+ UINT8 TriggerSWErrThEn;
+
+/** SW Per Row Threshold
+ SW Per Row Correctable Error Threshold (1 - 0x7FFF) used for row level error.
+**/
+ UINT16 SparePerRowTh;
+
/** N/A
**/
- UINT8 ReservedSiliconInitUpd[16];
+ UINT8 ReservedSmmInitUpd[16];
} FSPI_CONFIG;
@@ -87,11 +302,15 @@ typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
+/** N/A
+**/
+ FSPI_ARCH_UPD FspiArchUpd;
+
/** N/A
**/
FSPI_CONFIG FspiConfig;
-
+
/** N/A
**/
UINT16 UpdTerminator;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h
index c0f09df54d..74df875686 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -30,656 +30,637 @@ are permitted provided that the following conditions are met:
**/
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
+#ifndef __FSPM_UPD_H__
+#define __FSPM_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
-
-/** FSP-M Configuration
-**/
typedef struct {
-/** Offset 0x0040 - Customer Revision
+/** Customer Revision
The Customer can set this revision string for their own purpose.
**/
UINT8 CustomerRevision[32];
-/** Offset 0x0060 - Bus Ratio
+/** Bus Ratio
Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
**/
UINT8 BusRatio[8];
-/** Offset 0x0068 - D2K Credit Config
- Set the D2K Credit Config - 1: Min, <b>2: Med(Default)</b>, 3: Max.
- 1:Min, 2:Med, 3:Max
-**/
- UINT8 D2KCreditConfig;
-
-/** Offset 0x0069 - Snoop Throttle Config
- Set the Snoop Throttle Config - <b>0: DIS(Default)</b>, 1: Min, 2: Med, 3: Max.
- 0:DIS, 1:Min, 2:Med, 3:Max
-**/
- UINT8 SnoopThrottleConfig;
-
-/** Offset 0x006A - Legacy VGA Soc
+/** Legacy VGA Soc
Socket that claims the legacy VGA range
**/
UINT8 LegacyVgaSoc;
-/** Offset 0x006B - Legacy VGA Stack
+/** Legacy VGA Stack
Stack that claims the legacy VGA range
**/
UINT8 LegacyVgaStack;
-/** Offset 0x006C - Pcie P2P Performance Mode
- Determine if to enable PCIe P2P Performance Mode - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Pcie P2P Performance Mode
+ Determine if to enable PCIe P2P Performance Mode
+ $EN_DIS
**/
UINT8 P2pRelaxedOrdering;
-/** Offset 0x006D - UPI Debug Print Level
- UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8:
- Detail, <b>0x0F: All(Default)</b>.
+/** UPI Debug Print Level
+ UPI Debug Print Level Bitmask. 0- Disable, 1- Fatal, 2- Warning, 4- Summary, 8-
+ Detail, <b>0xF- All(Default)</b>
1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
**/
UINT8 DebugPrintLevel;
-/** Offset 0x006E - NumaEn
- NumaEn - <b>1: Enable Numa(Default)</b>, 0: Disable Numa.
- 0:Disable, 1:Enable
+/** NumaEn
+ Enable or Disable Numa
+ $EN_DIS
**/
UINT8 NumaEn;
-/** Offset 0x006F - SNC
- Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, <b>0x0F: Auto(Default)</b>.
- 0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto
+/** SNC Enable
+ Enable or Disable SNC
+ 0x0:Disable, 0x1:Enable, 0x0F:Auto
**/
UINT8 SncEn;
-/** Offset 0x0070 - UMA Clustering
- Set UMA Clusters - 0: Disable, 2: Two Clusters, <b>4: Four Clusters(Default)</b>.
- 0:Disable, 2:Two Clusters, 4:Four Clusters
-**/
- UINT8 UmaClustering;
-
-/** Offset 0x0071 - IODC Mode
- IODC Mode - 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow, 4: NonAlloc,
- 5: WCILF.
+/** IODC Mode
+ IODC Mode. 0- Disable, <b>1- Auto(Default)</b>, 2- Push, 3- AllocFlow, 4- NonAlloc, 5- WCILF
0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
**/
UINT8 IoDcMode;
-/** Offset 0x0072 - Degrade Precedence
- Setup Degrade Precedence - <b>0: Topology(Default)</b>, 1: Feature.
+/** Degrade Precedence
+ Setup Degrade Precedence
0:Topology, 1:Feature
**/
UINT8 DegradePrecedence;
-/** Offset 0x0073 - Degrade 4 Socket Preference
- Setup Degrade 4 Socket Preference - <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring.
+/** Degrade 4 Socket Preference
+ Setup Degrade 4 Socket Preference
0:Fully Connect, 1:Dual Link Ring
**/
UINT8 Degrade4SPreference;
-/** Offset 0x0074 - Directory Mode
- Enable or Disable Directory Mode - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** Directory Mode
+ Enable or Disable Directory Mode
0:Disable, 1:Enable, 2:Auto
**/
UINT8 DirectoryModeEn;
-/** Offset 0x0075 - XPT Prefetch Enable
- Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** XPT Prefetch Enable
+ Enable or Disable XPT Prefetch
0:Disable, 1:Enable, 2:Auto
**/
UINT8 XptPrefetchEn;
-/** Offset 0x0076 - KTI Prefetch Enable
- Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** KTI Prefetch Enable
+ Enable or Disable KTI Prefetch
0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiPrefetchEn;
-/** Offset 0x0077 - XPT Remote Prefetch Enable
- Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+/** XPT Remote Prefetch Enable
+ Enable or Disable XPT Remote Prefetch Enable
0:Disable, 1:Enable, 2:Auto
**/
UINT8 XptRemotePrefetchEn;
-/** Offset 0x0078 - KTI FPGA
- Enable or Disable KTI FPGA
+/** Distress QoS Mode
+ Distress QoS. <b>0- Mode 0(Default)</b>, 2- Mode 2
+ 0:Mode 0, 2:Mode 2
**/
- UINT8 KtiFpgaEnable[8];
+ UINT8 DistressQoS;
-/** Offset 0x0080 - DDRT QoS Mode
- DDRT QoS - <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2.
- 0:Mode 0, 1:Mode 1, 2:Mode 2
-**/
- UINT8 DdrtQosMode;
-
-/** Offset 0x0081 - KTI Link Speed Mode
- Choose KTI Link Speed Mode - 0: Slow, <b>1: Full(Default)</b>.
+/** KTI Link Speed Mode
+ Choose KTI Link Speed Mode
0:Slow, 1:Full
**/
UINT8 KtiLinkSpeedMode;
-/** Offset 0x0082 - KTI Link Speed
- Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, <b>0x7F: Max KTI
- Link Speed (Default)</b>, 0x8F: Frequency Per Link.
- 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
+/** KTI Link Speed
+ Setup KTI Link Speed - 2- 160GT, 3- 200GT, 4- 240GT, <b>0x7F- Max KTI Link Speed
+ (Default)</b>, 0x8F- Frequency Per Link
+ 2:160GT, 3:200GT, 4:240GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
**/
UINT8 KtiLinkSpeed;
-/** Offset 0x0083 - KTI Link L0p
- Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Link L0p
+ Enable or Disable KTI Link L0p
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiLinkL0pEn;
-/** Offset 0x0084 - KTI Link L1
- Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Link L1
+ Enable or Disable KTI Link L1
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiLinkL1En;
-/** Offset 0x0085 - Kti Link Speed Per Port
- Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT,
- 3: 200GT, <b>0x7f: Max KTI Link Speed(Default)</b>.
- 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed
+/** Kti Link Speed Per Port
+ Setup KTI Link Speed to be allocated for each port, 2:160GT, 2:200GT, 3:240GT, 0X7f:Max
+ KTI Link Speed
**/
UINT8 KtiLinkSpeedPerPort[48];
-/** Offset 0x00B5 - DfxL0p Enable
- Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DfxL0p Enable
+ Indicates the DfxL0p Enable to be allocated for each port, 0:Disable, 1:Enable
**/
UINT8 DfxL0pEnable[48];
-/** Offset 0x00E5 - DfxL1 Enable
- Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DfxL1 Enable
+ Indicates the DfxL1 Enable to be allocated for each port, 0:Disable, 1:Enable
**/
UINT8 DfxL1Enable[48];
-/** Offset 0x0115 - KTI Failover
- Enable or Disable KTI Failover - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2: Auto
+/** KTI Failover
+ Enable or Disable KTI Failover
+ 0:Disable, 1:Enable, 2:Auto
**/
UINT8 KtiFailoverEn;
-/** Offset 0x0116 - KTI LB Enable
- Enable or Disable KTI LB - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
-**/
- UINT8 KtiLbEn;
-
-/** Offset 0x0117 - KTI CRC Mode
- Select KTI CRC Mode - <b>0: 16bit(Default)</b>, 1: 32bit, 2: Auto.
+/** KTI CRC Mode
+ Select KTI CRC Mode
0:16bit, 1:32bit, 2:Auto
**/
UINT8 KtiCrcMode;
-/** Offset 0x0118 - KTI CPU Socket Hotplug
- Enable or Disable KTI CPU Socket Hotplug - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** KTI CPU Socket Hotplug
+ Enable or Disable KTI CPU Socket Hotplug
+ $EN_DIS
**/
UINT8 KtiCpuSktHotPlugEn;
-/** Offset 0x0119 - KTI CPU Socket HotPlug Topology
- Select KTI CPU Socket HotPlug Topology - <b>0: 4Socket(Default)</b>, 1: 8Socket.
+/** KTI CPU Socket HotPlug Topology
+ Select KTI CPU Socket HotPlug Topology
0:4Socket, 1:8Socket
**/
UINT8 KtiCpuSktHotPlugTopology;
-/** Offset 0x011A - KTI SKU Mismatch Check
- Enable or Disable KTI SKU Mismatch Check - 0: Disable, <b>1 :Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** KTI SKU Mismatch Check
+ Enable or Disable KTI SKU Mismatch Check
+ $EN_DIS
**/
UINT8 KtiSkuMismatchCheck;
-/** Offset 0x011B - TOR Threshold - Loctorem threshold Normal
- Select TOR Threshold - Loctorem threshold Normal - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Low, 3: Medium, 4: High.
+/** Sdsi Contrl Ib Lock
+ Enable or Disable Sdsi Contrl Ib Lock
+ $EN_DIS
+**/
+ UINT8 SdsiCtrlIbLock;
+
+/** TOR Threshold - Loctorem threshold Normal
+ Select TOR Threshold - Loctorem threshold Normal
0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
**/
UINT8 TorThresLoctoremNorm;
-/** Offset 0x011C - TOR threshold - Loctorem threshold empty
- Select TOR threshold - Loctorem threshold empty - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Low, 3: Medium, 4:High.
+/** TOR threshold - Loctorem threshold empty
+ Select TOR threshold - Loctorem threshold empty
0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
**/
UINT8 TorThresLoctoremEmpty;
-/** Offset 0x011D - TSC Sync in Sockets
- Enable or Disable TSC Sync in Sockets - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 TscSyncEn;
-
-/** Offset 0x011E - HA A to S directory optimization
- Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, <b>2:
- Auto(Default)</b>.
+/** HA A to S directory optimization
+ Enable or Disable HA A to S directory optimization
0:Disable, 1:Enable, 2:Auto
**/
UINT8 StaleAtoSOptEn;
-/** Offset 0x011F - LLC Deadline Allocation
- Enable or Disable LLC Deadline Allocation - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
+/** LLC Deadline Allocation
+ Enable or Disable LLC Deadline Allocation
0:Disable, 1:Enable, 2:Auto
**/
UINT8 LLCDeadLineAlloc;
-/** Offset 0x0120 - MBA BW Calibration Profiles
- Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping,
- 2: Legacy BW shaping, <b>3: Auto(Default)</b>.
+/** MBA BW Calibration Profiles
+ Choice of MBA BW throttling curve
0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
**/
UINT8 MbeBWCalChoice;
-/** Offset 0x0121 - Split Lock
- Enable or Disable Split Lock - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
+/** PMM MBA BW downscale
+ PMM BW downscaling vs the baseline Total memory BW profile. Eg- picking 1/2x results
+ in scaling PMM BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:PMM BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
**/
- UINT8 SplitLock;
+ UINT8 PmmMbaBWDownscale;
-/** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket
- Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0:
- Disable, 1: Enable, <b>2: Auto(Default)</b>.
- 0:Disable, 1:Enable, 2:Auto
+/** CXL (Type3) MBA BW downscale
+ CXL (Type3) BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling CXL (Type3) BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:CXL BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
**/
- UINT8 M2iosfToUpiAffinity;
+ UINT8 CxlMbaBWDownscale;
-/** Offset 0x0123 - MMCFG Base Address
- Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, <b>6:
- Auto(Default)</b>.
- 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto
+/** Remote Target MBA BW downscale
+ Remote Target BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling Remote Target BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:Remote Target BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1
+ ratio, 3:8/1 ratio
**/
- UINT8 mmCfgBase;
+ UINT8 RemoteTargetMbaBWDownscale;
-/** Offset 0x0124 - MMCFG Size
- Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, <b>6: Auto(Default)</b>.
- 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto
+/** Split Lock
+ Enable or Disable Split Lock
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 mmCfgSize;
+ UINT8 SplitLock;
-/** Offset 0x0125
+/** MMCFG Base Address
+ Setup MMCFG Base Address
+ 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 0xFF:Auto
**/
- UINT8 UnusedUpdSpace0[3];
+ UINT32 mmCfgBase;
-/** Offset 0x0128 - MMIO High Base Address
- MMIO High Base Address, a hex number for Bit[51:32]
+/** MMCFG Size
+ Select MMCFG Size
+ 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 0xFF:Auto
**/
- UINT32 mmiohBase;
+ UINT32 mmCfgSize;
-/** Offset 0x012C - CPU Physical Address Limit
- CPU Physical Address Limit - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** MMIO High Base Address
+ MMIO High Base Address
+ 0:56T, 1:40T, 2:32T, 3:24T, 4:16T, 5:4T, 6:2T, 7:1T, 8:512G, 9:3584T, 10:30T, 11:60T,
+ 12:88T, 13:120T, 14:248T, 255:AUTO
**/
- UINT8 CpuPaLimit;
+ UINT32 mmiohBase;
-/** Offset 0x012D
+/** CPU Physical Address Limit
+ CPU Physical Address Limit
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace1;
+ UINT8 CpuPaLimit;
-/** Offset 0x012E - MMIO High Size
- MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
- per CPU. Range 1-1024
+/** MMIO High Size
+ MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU.
+ 0:1GB, 1:4GB, 2:16GB, 3:64GB, 4:256GB, 5:1024GB, 6:32GB, 255:AUTO
**/
- UINT16 mmiohSize;
+ UINT32 mmiohSize;
-/** Offset 0x0130 - isocEn
- Enable or Disable isocEn - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 isocEn;
-
-/** Offset 0x0131 - DCA
- Enable or Disable DCA - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** DCA
+ Enable or Disable DCA
+ $EN_DIS
**/
UINT8 dcaEn;
-/** Offset 0x0132
-**/
- UINT8 UnusedUpdSpace2[2];
-
-/** Offset 0x0134 - BoardTypeBitmask
+/** BoardTypeBitmask
BoardTypeBitmask
**/
UINT32 BoardTypeBitmask;
-/** Offset 0x0138 - AllLanesPtr
+/** S3mClkSetupPtr
+ Pointer to clk setup variable data
+**/
+ UINT64 S3mClkSetupPtr;
+
+/** AllLanesPtr
Pointer to array of ALL_LANES_EPARAM_LINK_INFO
**/
- UINT32 AllLanesPtr;
+ UINT64 AllLanesPtr;
-/** Offset 0x013C - PerLanePtr
+/** PerLanePtr
Pointer to array of PER_LANE_EPARAM_LINK_INFO
**/
- UINT32 PerLanePtr;
+ UINT64 PerLanePtr;
-/** Offset 0x0140 - AllLanesSizeOfTable
+/** AllLanesSizeOfTable
Number of elements in AllLanesPtr array.
**/
UINT32 AllLanesSizeOfTable;
-/** Offset 0x0144 - PerLaneSizeOfTable
+/** PerLaneSizeOfTable
Number of elements in PerLanePtr array.
**/
UINT32 PerLaneSizeOfTable;
-/** Offset 0x0148 - WaitTimeForPSBP
+/** WaitTimeForPSBP
Enable or Disable WaitTimeForPSBP
**/
UINT32 WaitTimeForPSBP;
-/** Offset 0x014C - WaSerializationEn
- Enable or Disable WaSerializationEn - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
-**/
- UINT8 WaSerializationEn;
-
-/** Offset 0x014D - KtiInEnableMktme
- Enable or Disable KtiInEnableMktme - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** KtiInEnableMktme
+ Enable or Disable KtiInEnableMktme
+ $EN_DIS
**/
UINT8 KtiInEnableMktme;
-/** Offset 0x014E - HIOP STACK DISABLE
+/** HIOP STACK DISABLE
Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
the bit locations are not modified. The stack order is abstracted each bit 0 =
stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
- BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32.
+ BIOS based on part-knob compatibility. The array size must be MAX_SOCKET(Maximum:8) x UINT32.
**/
- UINT8 StackDisableBitMap[32];
+ UINT32 StackDisableBitMap[8];
-/** Offset 0x016E - CFRS3mProvision
- Enable or Disable Provision S3M CFR - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Processor VmxEnable Function
+ Enable(Default) or Disable Processor VmxEnable Function
+ $EN_DIS
**/
- UINT8 CFRS3mProvision;
+ UINT8 VmxEnable;
-/** Offset 0x016F - CFRS3mManualCommit
- Enable or Disable Manual Commit S3M FW CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Smm Relocation
+ Enable(Default)/Disable Smm Relocation
+ $EN_DIS
**/
- UINT8 CFRS3mManualCommit;
+ UINT8 SmmRelocationEnable;
-/** Offset 0x0170 - CFRPucodeProvision
- Enable or Disable Provision PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Processor HyperThreading Function
+ Enables Logical processor, 0- ALL LPs, 1- Single LP, 2- Two LPs
+ 0:ALL LPs, 1:Single LP, 2:Two LPs
**/
- UINT8 CFRPucodeProvision;
+ UINT8 ProcessorLpEnable;
-/** Offset 0x0171 - CFRPucodeManualCommit
- Enable or Disable Manual Commit PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Processor Safer Mode Extensions Function
+ Enable or Disable(Default) Processor Safer Mode Extensions Function
+ $EN_DIS
**/
- UINT8 CFRPucodeManualCommit;
+ UINT8 ProcessorSmxEnable;
-/** Offset 0x0172
+/** Uncore Freq Ratio Compute
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
**/
- UINT8 UnusedUpdSpace3[2];
+ UINT8 UncoreFreqRatio;
-/** Offset 0x0174 - CFRImagePtr
- Pointer to array of CFR Image
+/** Uncore Freq Ratio IO
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
**/
- UINT32 CFRImagePtr;
+ UINT8 UncoreFreqRatioIo;
-/** Offset 0x0178 - Processor VmxEnable Function
- Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DDR frequency limit
+ Select DDR frequency limit, <b>0x00- Auto(Default)</b>, 0x01:DDR_3200, 0x03:DDR_3600,
+ 0x05:DDR_4000, 0x07:DDR_4400, 0x08:DDR_4800, 0x09:DDR_5200, 0x0A:DDR_5600, 0x0B:DDR_6000,
+ 0x0C:DDR_6400
**/
- UINT8 VmxEnable;
+ UINT8 HostDdrFreqLimit;
-/** Offset 0x0179 - Processor X2apic Function
- Enable(Default) or Disable Processor X2apic Function - 0: Disable, <b>1: Enable(Default)</b>.
+/** DDR Over Clock Enable
+ DDR Over Clock Enable, 0- Disable, 1- Enable
0:Disable, 1:Enable
**/
- UINT8 X2apic;
+ UINT8 DdrOverClockEnable;
-/** Offset 0x017A - Processor HyperThreading Function
- Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, <b>0:
- Enable(Default)</b>.
- 1:Disable, 0:Enable
+/** Advanced Debug Function
+ Select Advanced Debug Function, 0- Disable, 1- Enable, 2- Auto
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 ProcessorHyperThreadingDisable;
+ UINT8 DfxAdvDebugJumper;
-/** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function
- Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function -
- <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** Memory Serial Debug Message Level
+ Select Memory Serial Debug Message Level, 0- Disable, 1- Minimum, 2- Normal, 3-
+ Maximum, <b>4- Auto(Default)</b>, 5- Fixed PCD
+ 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto, 5:Fixed PCD
**/
- UINT8 ProcessorDynamicIssEnable;
+ UINT8 serialDebugMsgLvl;
-/** Offset 0x017C - Enables Intel(R) TXT
- Enable or Disable(Default) Enables Intel(R) TXT - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** IIO IioPE0Bifurcation
+ IioPE0Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 ProcessorLtsxEnable;
+ UINT8 IioPE0Bifurcation[8];
-/** Offset 0x017D - DDR frequency limit
- Select DDR frequency limit, <b>0x00: Auto(Default)</b>, 0x13:DDR_3200, 0x16:DDR_3600,
- 0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600
+/** IIO IioPE1Bifurcation
+ IioPE1Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 DdrFreqLimit;
+ UINT8 IioPE1Bifurcation[8];
-/** Offset 0x017E - Memory Serial Debug Message Level
- Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, <b>3:
- Maximum(Default)</b>, 4: Auto.
- 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto
+/** IIO IioPE2Bifurcation
+ IioPE2Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 serialDebugMsgLvl;
+ UINT8 IioPE2Bifurcation[8];
-/** Offset 0x017F - IIO ConfigIOU0
- ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE3Bifurcation
+ IioPE3Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU0[8];
+ UINT8 IioPE3Bifurcation[8];
-/** Offset 0x0187 - IIO ConfigIOU1
- ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE4Bifurcation
+ IioPE4Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU1[8];
+ UINT8 IioPE4Bifurcation[8];
-/** Offset 0x018F - IIO ConfigIOU2
- ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPE5Bifurcation
+ IioPE5Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU2[8];
+ UINT8 IioPE5Bifurcation[8];
-/** Offset 0x0197 - IIO ConfigIOU3
- ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEaBifurcation
+ IioPEaBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU3[8];
+ UINT8 IioPEaBifurcation[8];
-/** Offset 0x019F - IIO ConfigIOU4
- ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEbBifurcation
+ IioPEbBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU4[8];
+ UINT8 IioPEbBifurcation[8];
-/** Offset 0x01A7 - IIO ConfigIOU5
- ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEcBifurcation
+ IioPEcBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU5[8];
+ UINT8 IioPEcBifurcation[8];
-/** Offset 0x01AF - IIO ConfigIOU6
- ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+/** IIO IioPEdBifurcation
+ IioPEdBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
**/
- UINT8 IioConfigIOU6[8];
+ UINT8 IioPEdBifurcation[8];
+
+/** IIO PCIE MaxPayload Ptr
+ Pointer to array of PCIE MaxPayload settings Per Port
+**/
+ UINT32 IioPcieMaxPayloadPtr;
+
+/** IIO PCIE MaxPayload entry Number
+ Number of elements in PcieMaxPayloadPtr array, port number as unit.
+**/
+ UINT32 IioPcieMaxPayloadNumber;
+
+/** IIO Board settings Hob Ptr
+ Pointer to array of IIO_BOARD_SETTINGS_HOB
+**/
+ UINT32 IioBoardSettingsHobPtr;
+
+/** IIO Board Settings Hob length
+ The IIO Board Settings Hob Length.
+**/
+ UINT32 IioBoardSettingsHobLength;
+
+/** Iio Setup Knobs pointer
+ : Iio Setup Knobs pointer
+**/
+ UINT64 IioSetupKnobsPtr;
-/** Offset 0x01B7
+/** Iio Setup Knobs Size
+ : Iio Setup Knobs Size
**/
- UINT8 UnusedUpdSpace4;
+ UINT64 IioSetupKnobsSize;
-/** Offset 0x01B8 - IIO PCIE Config Table Ptr
- Pointer to array of UPD_IIO_PCIE_PORT_CONFIG
+/** Iio SocketConfig Setup Knobs pointer
+ : Iio SocketConfig Setup Knobs pointer
**/
- UINT32 IioPcieConfigTablePtr;
+ UINT64 IioSocketConfigSetupKnobsPtr;
-/** Offset 0x01BC - IIO PCIE Config Table Number
- Number of elements in IioPcieConfigTablePtr array, socket number as unit.
+/** Iio SocketConfig Setup Knobs Size
+ : Iio SocketConfig Setup Knobs Size
**/
- UINT32 IioPcieConfigTableNumber;
+ UINT64 IioSocketConfigSetupKnobsSize;
-/** Offset 0x01C0 - IIO DeEmphasis Array Ptr
+/** IIO DeEmphasis Array Ptr
Pointer to array of DeEmphasis
**/
UINT32 DeEmphasisPtr;
-/** Offset 0x01C4 - IIO DeEmphasis Array Number
+/** IIO DeEmphasis Array Number
Number of elements in DeEmphasis array.
**/
UINT32 DeEmphasisNumber;
-/** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr
+/** IIO PCIe Common Clock Array Ptr
Pointer to array of PCIe Common Clock
**/
UINT32 PcieCommonClockPtr;
-/** Offset 0x01CC - IIO PCIe Common Clock Array Number
+/** IIO PCIe Common Clock Array Number
Number of elements in PCIe Common Clock array.
**/
UINT32 PcieCommonClockNumber;
-/** Offset 0x01D0 - VT-d Support
- Enable or Disable VT-d Support - 0: Disable, <b>1: Enable(Default)</b>.
+/** Gen5LinkDegradation
+ Enable or disable Gen5 link degradation.
0:Disable, 1:Enable
**/
- UINT8 VtdSupport;
+ UINT8 Gen5LinkDegradation;
-/** Offset 0x01D1 - PCIe ACSCTL
- Enable/Disable overwrite of PCI Access Control Services Control register in PCI
- root ports - 0: Disable, <b>1: Enable(Default)</b>.
+/** PcieHotPlugEnable
+ Enable or disable Pcie hot plug enable feature
0:Disable, 1:Enable
**/
- UINT8 VtdPciAcsCtlWaEn;
-
-/** Offset 0x01D2
-**/
- UINT8 UnusedUpdSpace5[2];
+ UINT8 PcieHotPlugEnable;
-/** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr
- Pointer to array of Hide or visible for IIO Pcie Port.
+/** DelayAfterPCIeLinkTraining
+ Custom delay after PCI-E link training on IIO ports
**/
- UINT32 PEXPHIDEPtr;
+ UINT16 DelayAfterPCIeLinkTraining;
-/** Offset 0x01D8 - IIO PCIe Port Hide Array Number
- Number of elements in IIO PCIe Port Hide Array.
+/** MSR Lock Control
+ Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
+ remove lock bits
+ 0:Disable, 1:Enable
**/
- UINT32 PEXPHIDENumber;
+ UINT8 ProcessorMsrLockControl;
-/** Offset 0x01DC - PcieHotPlugEnable
- Enable or disable Pcie hot plug enable feature - <b>0: Disable(Default)</b>, 1: Enable.
+/** Lock Chipset
+ Lock or Unlock chipset in FSP
0:Disable, 1:Enable
**/
- UINT8 PcieHotPlugEnable;
+ UINT8 LockChipset;
-/** Offset 0x01DD
+/** DFX Ev Mode
+ When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 UnusedUpdSpace6;
+ UINT8 DfxEvMode;
-/** Offset 0x01DE - DelayAfterPCIeLinkTraining
- Custom delay after PCI-E link training on IIO ports
+/** DFX Disable Bios Done
+ When Enabled, suppresses notifying processor via MSR 151h that boot initialization
+ is finished in FSP
+ 0:Disable, 1:Enable
**/
- UINT16 DelayAfterPCIeLinkTraining;
+ UINT8 DfxDisableBiosDone;
-/** Offset 0x01E0 - IIO PCI bus resource Ptr
+/** PciBusResConfigPtr
Pointer to array of socket PCI bus resource.
**/
UINT32 PciBusResConfigPtr;
-/** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr
+/** PciBaseLimitsResConfigPtr
Pointer to array of socket PCI IO/MMIO resource.
**/
UINT32 PciBaseLimitsResConfigPtr;
-/** Offset 0x01E8 - PCH PCIE PLL Ssc
- Pointer to array of socket PCI IO/MMIO resource.
+/** PCH PCIE PLL Ssc
**/
UINT8 PchPciePllSsc;
-/** Offset 0x01E9 - MeUmaEnable
- Enable or disable ME UMA feature - <b>0: Disable(Default)</b>, 1: Enable.
+/** PchDciEn
+ Enable or <b>Disable(Default)</b> PCH DCI
0:Disable, 1:Enable
**/
- UINT8 MeUmaEnable;
+ UINT8 PchDciEn;
-/** Offset 0x01EA - SerialIoUartDebugEnable
- Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, <b>1: Enable(Default)</b>.
+/** MeUmaEnable
+ Enable or disable ME UMA feature
0:Disable, 1:Enable
**/
- UINT8 SerialIoUartDebugEnable;
+ UINT8 MeUmaEnable;
-/** Offset 0x01EB
+/** SerialIoUartDebugEnable
+ <b>Enable(Default)</b> or Disable SerialIo Uart debug library in FSP.
+ 0:Disable, 1:Enable
**/
- UINT8 UnusedUpdSpace7;
+ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x01EC - ISA Serial Base selection
- Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8,
- <b>0x3F8: 0x3F8(Default)</b>.
+/** ISA Serial Base selection
+ Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
0x2F8:0x2F8, 0x3F8:0x3F8
**/
UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x01EE - MemRefreshWaterMark
- Enable or Disable MemRefreshWaterMark in FSP - <b>0: Auto(Default)</b>, 1: Enable,
- 2: Disable.
- 0:Auto, 1:Enable, 2:Disable
-**/
- UINT8 PanicWm;
-
-/** Offset 0x01EF - promoteMrcWarnings
- Enable or Disable MRC promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** promoteMrcWarnings
+ Determines if MRC warnings are promoted to system level in FSP.
+ $EN_DIS
**/
UINT8 promoteMrcWarnings;
-/** Offset 0x01F0 - promoteWarnings
- <b>Enable(Default)</b> or Disable Promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** promoteWarnings
+ Determines if warnings are promoted to system level in FSP.
+ $EN_DIS
**/
UINT8 promoteWarnings;
-/** Offset 0x01F1 - serialDebugMsgLvlTrainResults
- Enable or Disable Promote warning in FSP - <b>0:Disable(Default)</b>, 8:Enable.
- 0:Disable, 8:Enable
+/** serialDebugMsgLvlTrainResults
+ Enabled = set to display the training results. Training results also get displayed
+ if debug messages is set to Maximum in FSP.
+ $EN_DIS
**/
UINT8 serialDebugMsgLvlTrainResults;
-/** Offset 0x01F2 - MemTest
- <b>Enable(Default)</b> or Disable memory test during normal boot in FSP - 0: Disable,
- <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Enhanced Log Parsing
+ Enables additional output in debug log for easier machine parsing in FSP.
+ $EN_DIS
**/
- UINT8 HwMemTest;
+ UINT8 logParsing;
-/** Offset 0x01F3
+/** MemTest
+ Enable - Enables memory test during normal boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace8;
+ UINT8 HwMemTest;
-/** Offset 0x01F4 - MemTest Loops
- Number of memory test loops during normal boot, set to 0 to run memtest infinitely
- in FSP - <b> 1 (Default)</b>.
- minimum = 0, maximum = 65535
+/** MemTest Loops
+ Number of memory test loops during normal boot, set to 0 to run memtest infinitely in FSP.
**/
UINT16 MemTestLoops;
-/** Offset 0x01F6
-**/
- UINT8 UnusedUpdSpace9[2];
-
-/** Offset 0x01F8 - Adv MemTest Options
- This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16,
+/** Adv MemTest Options
+ This option is a bit mask[19:0]- All 0 = disabled- bit-0=XMATS8, bit-1=XMATS16,
bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
@@ -687,627 +668,1149 @@ typedef struct {
**/
UINT32 AdvMemTestOptions;
-/** Offset 0x01FC - SmartTestKey
+/** SmartTestKey
Number of SmartTest Key
**/
UINT32 SmartTestKey;
-/** Offset 0x0200 - Adv MemTest Pause
- Specify a pause delay between 0 to 256000 in units of usec. This is a time period
- where refresh is disabled between write and read sequences in FSP.
+/** Adv MemTest Pause
+ Specify a pause delay between 0 to 255 in units of msec. This is a time period where
+ refresh is disabled between write and read sequences in FSP.
**/
- UINT32 AdvMemTestCondPause;
+ UINT8 AdvMemTestCondPause;
-/** Offset 0x0204 - Adv MemTest tREFI
+/** Adv MemTest tREFI
Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
**/
UINT16 AdvMemTestCondTrefi;
-/** Offset 0x0206 - Adv MemTest tWR
- Specify tWR timing between 48 to 96 in units of tCK in FSP.
+/** Adv MemTest tWR
+ Specify tWR timing between 48 to 96 in units of tCK in FSP.
**/
UINT8 AdvMemTestCondTwr;
-/** Offset 0x0207
-**/
- UINT8 UnusedUpdSpace10;
-
-/** Offset 0x0208 - Adv MemTest PMIC VDD Level
+/** Adv MemTest PMIC VDD Level
Specify PMIC VDD level in units of mV in FSP.
**/
UINT16 AdvMemTestCondPmicVdd;
-/** Offset 0x020A - Adv MemTest Conditions
+/** Adv MemTest Conditions
Auto = set test conditions based on test type; Manual = specify global test conditions;
- Disable = Do not apply test conditions in FSP - 0: Disable, <b>1: Auto(Default)</b>,
- 2: Manual.
+ Disable = Do not apply test conditions in FSP.
0:Disable, 1:Auto, 2:Manual
**/
UINT8 AdvMemTestCondition;
-/** Offset 0x020B - Adv MemTest Reset Failure Tracking List
+/** Adv MemTest Reset Failure Tracking List
Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
- Useful for testing performance of multiple options in FSP - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+ Useful for testing performance of multiple options in FSP.
+ $EN_DIS
**/
UINT8 AdvMemTestResetList;
-/** Offset 0x020C - MemTest On Cold Fast Boot
- Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
- Auto - Sets it to the MRC default setting; current default is Disable in FSP -
- <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 MemTestOnColdFastBoot;
-/** Offset 0x020D - Attempt Fast Boot
+/** Attempt Fast Boot
Enable - Portions of memory reference code will be skipped when possible to increase
- boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the
- MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+ boot speed on warm boots. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 AttemptFastBoot;
-/** Offset 0x020E - MemTest On Cold Fast Boot
- Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
- Auto - Sets it to the MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
**/
UINT8 AttemptFastBootCold;
-/** Offset 0x020F - Multithreaded Memory Training
- Selects the number of processor sockets to train in parallel. - <b>0: All sockets
- operate in parallel(Default)</b>. 1: At any time only one socket is executing.
- 2: At any time only two socket are executing. 4: At any time only four socket are
- executing in FSP.
+/** Multithreaded Memory Training
+ Selects the number of processor sockets to train in parallel. 0 - All sockets operate
+ in parallel. 1 - At any time only one socket is executing. 2 - At any time only
+ two socket are executing. 4 - At any time only four socket are executing in FSP.
0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
at a Time, 4:Four Sockets at a Time
**/
UINT8 AllowedSocketsInParallel;
-/** Offset 0x0210 - Auto-Reset on mem Training Error
- Enable/Disable Auto-Reset on mem Training Error in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** Auto-Reset on mem Training Error
+ Enable/Disable Auto-Reset on mem Training Error in FSP.
+ $EN_DIS
**/
UINT8 AutoResetOnMemErr;
-/** Offset 0x0211 - Rank Margin Tool
- Enable/Disable the Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Rank Margin Tool
+ Enable/Disable two types of rank margin in FSP.
+ 0:Normal RMT & Turnaround RMT Disabled, 1:Normal RMT Enabled, 2:Turnaround RMT Enabled,
+ 3:Normal RMT & Turnaround RMT Enabled, 4:Auto RMT Enable/Disabled
**/
UINT8 EnableRMT;
-/** Offset 0x0212 - RMT on Fast Cold Boot
- Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** RMT on Fast Cold Boot
+ Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP.
+ $EN_DIS
**/
UINT8 EnableRMTonFCB;
-/** Offset 0x0213 - Execute Jedecinit before RMT
- Execute Jedecinit before Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** Execute Jedecinit before RMT
+ Execute Jedecinit before Rank Margin Tool in FSP.
+ $EN_DIS
**/
UINT8 JedecInitBeforeRMT;
-/** Offset 0x0214 - Backside Margining
- Enable/Disable margin test on the register or buffer backside in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** Backside Margining
+ Enable/Disable margin test on the register or buffer backside in FSP.
+ $EN_DIS
**/
UINT8 RMTBacksideMargining;
-/** Offset 0x0215 - CmdAll
- Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
- 1:Auto, 2:2, 4:4, 8:8
+/** CmdAll
+ Step size of CmdAll. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:1, 2:2, 4:4, 8:8
**/
UINT8 RMTCmdAll;
-/** Offset 0x0216 - RMT Debug Messages
- Enable/Disable the RMT debug messages in FSP - <b>2:Disable(Default)</b>, 5:Enable.
+/** RMT Debug Messages
+ Enable/Disable the RMT debug messages in FSP.
2:Disable, 5:Enable
**/
UINT8 RMTDebugMessages;
-/** Offset 0x0217 - RMT Display Tables
- Enable/Disable displaying results as tables in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Display Tables
+ Enable/Disable displaying results as tables in FSP.
+ $EN_DIS
**/
UINT8 RMTDisplayTables;
-/** Offset 0x0218 - RMT Loop Count
+/** RMT Loop Count
Exponential loop count for single rank test in FSP.
**/
UINT8 RMTLoopCount;
-/** Offset 0x0219
-**/
- UINT8 UnusedUpdSpace11[3];
-
-/** Offset 0x021C - Test Signal Bit Mask For RMT
+/** Test Signal Bit Mask For RMT
Test signal bit mask for RMT in FSP.
**/
UINT32 TestSignalBitMaskRMT;
-/** Offset 0x0220 - RMT Per Bit Margining
- Enable/Disable Per Bit Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per Bit Margining
+ Enable/Disable Per Bit Margining in FSP.
+ $EN_DIS
**/
UINT8 RMTPerBitMargining;
-/** Offset 0x0221 - RMT Per CA Lane Margining
- Enable/Disable Per CA Lane Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per CA Lane Margining
+ Enable/Disable Per CA Lane Margining in FSP.
+ $EN_DIS
**/
UINT8 RMTPerCaLaneMargining;
-/** Offset 0x0222 - RMT Display Plots
- Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** RMT Per CS Lane Margining
+ Enable/Disable Per CS Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCsLaneMargining;
+
+/** RMT Display Plots
+ Enable/Disable the display of per-bit results as plots in FSP.
+ $EN_DIS
**/
UINT8 RMTPerDisplayPlots;
-/** Offset 0x0223 - RMT RxDqs
- Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
- 2:2, 4:4, 8:8.
+/** RMT RxDqs
+ Step size of RxDqs. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTRxDqs;
-/** Offset 0x0224 - RMT RxVref
- Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
- 2:2, 4:4, 8:8.
+/** RMT RxVref
+ Step size of RxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTRxVref;
-/** Offset 0x0225 - RMT Scrambler
- Enable or Disable scrambler during RMT test in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Dfx RMT Scrambler
+ Enable or Disable scrambler during RMT test in FSP.
+ $EN_DIS
**/
- UINT8 RMTScrambler;
+ UINT8 DfxScrambleEnRMT;
-/** Offset 0x0226 - RMT Step Size Override
- Enable or Disable overriding the default step sizes in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+/** RMT Step Size Override
+ Enable or Disable overriding the default step sizes in FSP.
+ $EN_DIS
**/
UINT8 RMTStepSizeOverride;
-/** Offset 0x0227 - RMT TxDq
- Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
+/** RMT TxDq
+ Step size of TxDq. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTTxDq;
-/** Offset 0x0228 - RMT TxVref
- Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
- 2:2, 4:4, 8:8.
+/** RMT TxVref
+ Step size of TxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
1:Auto, 2:2, 4:4, 8:8
**/
UINT8 RMTTxVref;
-/** Offset 0x0229 - DDR5 ECS
- Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** DDR5 ECS
+ Disable: Disable ECS/Result collection. Enable: Enable ECS without Result Collection.
+ Enable ECS with Result Collection: Enable ECS/Result Collection.
+ 0:Disable, 1:Enable, 2:Enable ECS with Result Collection
**/
UINT8 ErrorCheckScrub;
-/** Offset 0x022A - Enforce Memory POR
- 0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage
- programming. <b>2:Disable - Disables this feature and user is able to run at higher
- frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default)</b>.
- 0:Enforce POR, 2:Disabled
+/** Runtime PPR/Row Sparing
+ Enable/Disable Runtime PPR / Row Sparing.
+ $EN_DIS
+**/
+ UINT8 RtRowSparing;
+
+/** Mca Bank Warm Boot Clear Errors
+ Enable/Disable Mca Bank Warm Boot Clear Errors.
+ $EN_DIS
+**/
+ UINT8 McBankWarmBootClearError;
+
+/** RasStateVarPtr
+ Pointer to array of RAS_STATE_VARIABLE_DATA
+**/
+ UINT32 RasStateVarPtr;
+
+/** Enforce Memory POR
+ Enforce POR (0x0) - Enforces Plan Of Record restrictions for DDR5 frequency and
+ voltage programming. Enforce Stretch Goals (0x1) - Enforce DDR memory frequency
+ stretch goal. <b>Disable (0x2 - Default)</b> - Disables this feature and user is
+ able to run at higher frequencies, specified in the DDR Frequency Limit field (limited
+ by processor support).
+ 0:POR, 1:Enforce Stretch Goals, 2:Disabled
**/
UINT8 EnforceDdrMemoryFreqPor;
-/** Offset 0x022B - Enforce Population POR
+/** Enforce Population POR
Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations
- will only allow populations that have been validated in FSP - <b>0:Disable(Default)</b>,
- 1:Enable.
- 0:Disable, 1:Enable
+ will only allow populations that have been validated in FSP.
+ $EN_DIS
**/
UINT8 EnforcePopulationPor;
-/** Offset 0x022C - DDR PPR Type
- Selects DDR Post Package Repair Type - 2: Hard PPR, <b>1: Soft PPR (Default)</b>,
- 0: Disabled.
+/** DDR PPR Type
+ Selects DDR Post Package Repair Type - 2- Hard PPR, <b>1- Soft PPR (Default)</b>,
+ 0- Disabled.
0:Disabled, 2:Hard PPR, 1:Soft PPR
**/
UINT8 pprType;
-/** Offset 0x022D - Force PPR On All Dram for UCE
- Force PPR on all dram for UCE in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disabled, 1:Enabled
-**/
- UINT8 ForcePprOnAllDramUce;
-
-/** Offset 0x022E
-**/
- UINT8 UnusedUpdSpace12[2];
-
-/** Offset 0x0230 - pprAddrVariablePtr
+/** pprAddrVariablePtr
Pointer to array of PPR_ADDR_VARIABLE
**/
UINT32 PprAddrVariablePtr;
-/** Offset 0x0234 - Allow Memory Test Correctable Error
+/** BDAT ACPI Table
+ Enable / Disable publishing BDAT ACPI Table in FSP.
+ $EN_DIS
+**/
+ UINT8 bdatEn;
+
+/** Allow Memory Test Correctable Error
Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
- default setting; current default is Enable in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+ default setting; current default is Enable in FSP.
+ $EN_DIS
**/
UINT8 allowCorrectableMemTestError;
-/** Offset 0x0235 - Memory I/O Health Check
- Memory I/O Health Check - 0: Auto, 1: Manual, <b>2: Disable (Default)</b>. Select
- option Auto for default values. Manual for new values. Disable for disabling feature
- in FSP - 0:Auto, 1:Manual, <b>2:Disable(Default)</b>.
+/** SlotPerChannel
+ Slot number per channel, default value is 2
+ 1:Slot1, 2:Slot2
+**/
+ UINT8 SlotPerChannel;
+
+/** Memory I/O Health Check
+ Memory I/O Health Check - 0- Auto, 1- Manual, <b>2- Disable (Default)</b>. Select
+ option Auto for default values. Manual for new values. Disable for disabling feature in FSP.
0:Auto, 1:Manual, 2:Disable
**/
UINT8 MemIOHealthCheck;
-/** Offset 0x0236 - RxDqsDelay Left Edge
+/** Memory I/O Health Turnaround Test
+ Memory I/O Health Turnaround Test - 1- Enable, <b>0- Disable (Default)</b>. Select
+ Disable for disabling feature in FSP. Enable for enabling feature in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemIOHealthTurnaroundTest;
+
+/** Memory I/O Health Check Loop Count
+ CPGC Test Loop Count for Memory IO Health Test.
+**/
+ UINT8 MemIOLoopCount;
+
+/** RxDqsDelay Left Edge
Offset for RxDqsDelay Left Edge in FSP.
**/
UINT8 CriticalRxDqsDelayLeftEdge;
-/** Offset 0x0237 - RxDqsDelay Right Edge
+/** RxDqsDelay Right Edge
Offset for RxDqsDelay Right in FSP.
**/
UINT8 CriticalRxDqsDelayRightEdge;
-/** Offset 0x0238 - RxVref Left Edge
+/** RxVref Left Edge
Offset for RxVref Left Edge in FSP.
**/
UINT8 CriticalRxVrefLeftEdge;
-/** Offset 0x0239 - RxVref Right Edge
+/** RxVref Right Edge
Offset for RxVref Right Edge in FSP.
**/
UINT8 CriticalRxVrefRightEdge;
-/** Offset 0x023A - TxDqDelay Left Edge
+/** TxDqDelay Left Edge
Offset for TxDqDelay Left Edge in FSP.
**/
UINT8 CriticalTxDqDelayLeftEdge;
-/** Offset 0x023B - TxDqDelay Right Edge
+/** TxDqDelay Right Edge
Offset for TxDqDelay Right Edge in FSP.
**/
UINT8 CriticalTxDqDelayRightEdge;
-/** Offset 0x023C - TxVref Left Edge
+/** TxVref Left Edge
Offset for TxDqDelay Left Edge in FSP.
**/
UINT8 CriticalTxVrefLeftEdge;
-/** Offset 0x023D - TxVref Right Edge
+/** TxVref Right Edge
Offset for TxDqDelay Right Edge in FSP.
**/
UINT8 CriticalTxVrefRightEdge;
-/** Offset 0x023E - Reboot On Critical Failure
- Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Reboot On Critical Failure
+ Reboot System on Critical failure to do Memory Training in FSP.
+ $EN_DIS
**/
UINT8 ResetOnCriticalError;
-/** Offset 0x023F - Number of Times to Reboot and Retrain
+/** Number of Times to Reboot and Retrain
Number of times to Reboot System on Critical failure to do Memory Training in FSP.
**/
UINT8 CriticalRetries;
-/** Offset 0x0240 - Memory I/O Health Check Loop Count
- CPGC Test Loop Count for Memory IO Health Test
-**/
- UINT8 MemIOHealthLoopCount;
-
-/** Offset 0x0241 - Telemetry RxDqsDelay Left Edge
+/** Telemetry RxDqsDelay Left Edge
Offset for Telemetry RxDqsDelay Left Edge in FSP.
**/
UINT8 TelemetryRxDqsDelayLeftEdge;
-/** Offset 0x0242 - Telemetry RxDqsDelay Right Edge
+/** Telemetry RxDqsDelay Right Edge
Offset for Telemetry RxDqsDelay Right Edge in FSP.
**/
UINT8 TelemetryRxDqsDelayRightEdge;
-/** Offset 0x0243 - Telemetry RxVref Left Edge
+/** Telemetry RxVref Left Edge
Offset for Telemetry RxDqsDelay Left Edge in FSP.
**/
UINT8 TelemetryRxVrefLeftEdge;
-/** Offset 0x0244 - Telemetry RxVref Right Edge
+/** Telemetry RxVref Right Edge
Offset for Telemetry RxDqsDelay Right Edge in FSP.
**/
UINT8 TelemetryRxVrefRightEdge;
-/** Offset 0x0245 - Telemetry TxDqDelay Left Edge
+/** Telemetry TxDqDelay Left Edge
Offset for Telemetry TxDqDelay Left Edge in FSP.
**/
UINT8 TelemetryTxDqDelayLeftEdge;
-/** Offset 0x0246 - Telemetry TxDqDelay Right Edge
+/** Telemetry TxDqDelay Right Edge
Offset for Telemetry TxDqDelay Right Edge in FSP.
**/
UINT8 TelemetryTxDqDelayRightEdge;
-/** Offset 0x0247 - Volatile Memory Mode
- Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try
- to configure 2LM but if system is unable to configure 2LM, volatile memory mode
- will fall back to 1LM in FSP - <b>0: 1LM(Default)</b>, 1: 2LM, 2: MIX 1LM2LM.
- 0: 1LM, 1: 2LM, 2: MIX 1LM2LM
+/** Telemetry TxVref Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefLeftEdge;
+
+/** Telemetry TxVref Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefRightEdge;
+
+/** Telemetry CaTiming Left Edge
+ Offset for Telemetry CaTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingLeftEdge;
+
+/** Telemetry CaTiming Right Edge
+ Offset for Telemetry CaTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingRightEdge;
+
+/** Telemetry CtlTiming Left Edge
+ Offset for Telemetry CtlTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingLeftEdge;
+
+/** Telemetry CtlTiming Right Edge
+ Offset for Telemetry CtlTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingRightEdge;
+
+/** Telemetry CaVref Left Edge
+ Offset for Telemetry CaVref Left Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefLeftEdge;
+
+/** Telemetry CaVref Right Edge
+ Offset for Telemetry CaVref Right Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefRightEdge;
+
+/** Critical CaTiming Left Edge
+ Offset for Critical CaTiming Left Edge in FSP.
**/
- UINT8 volMemMode;
+ UINT8 CriticalCaTimingLeftEdge;
-/** Offset 0x0248 - Dynamic ECC Mode Selection
- Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, <b>1:Enable(Default)</b>,
- 2:Enable + Allow 128b ECC.
- 0:Disable, 1:Enable, 2:Enable + Allow 128b ECC
+/** Critical CaTiming Right Edge
+ Offset for Critical CaTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCaTimingRightEdge;
+
+/** Critical CtlTiming Left Edge
+ Offset for Critical CtlTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingLeftEdge;
+
+/** Critical CtlTiming Right Edge
+ Offset for Critical CtlTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingRightEdge;
+
+/** Critical CaVref Left Edge
+ Offset for Critical CaVref Left Edge in FSP.
+**/
+ UINT8 CriticalCaVrefLeftEdge;
+
+/** Critical CaVref Right Edge
+ Offset for Critical CaVref Right Edge in FSP.
+**/
+ UINT8 CriticalCaVrefRightEdge;
+
+/** Intel(R) Flat Memory Mode Support
+ Enable or disable Intel(R) Flat Memory Mode support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Flat2lmSupport;
+
+/** Dynamic ECC Mode Selection
+ Enable/Disable Dynamic ECC Mode Selection in FSP.
+ $EN_DIS
**/
UINT8 DynamicEccModeSel;
-/** Offset 0x0249 - Memory Patrol Scrub
- Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), <b>2:Enable during
- NotifyPhase(EnumInitPhaseReadyToBoot) (Default)</b>.
- 0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot
+/** Leaky bucket high bit
+ Leaky bucket high bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktHi;
+
+/** Leaky bucket time window based interface Hour
+ Leaky bucket time window based interface Hour" (0 - 24)
+**/
+ UINT16 leakyBktHour;
+
+/** Leaky bucket low bit
+ Leaky bucket low bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktLo;
+
+/** Leaky bucket time window based interface Minute
+ Leaky bucket time window based interface Minute" (0 - 60)
+**/
+ UINT8 leakyBktMinute;
+
+/** Leaky bucket time window based interface
+ Enable/Disable leaky bucket time window based interface
+ 0:Disable, 1:Enable
+**/
+ UINT8 leakyBktTimeWindow;
+
+/** Memory Patrol Scrub
+ Enable/Disable Patrol Scrub
+ 0:Disable, 2:Enable at End of POST
**/
UINT8 PatrolScrub;
-/** Offset 0x024A - Memory Patrol Scrub
+/** Memory Patrol Scrub Notify
Memory Patrol Scrub - <b>0:Disable (Default)</b>, 1:Enable at ReadyToBootFsp().
- 0:Disable, 1:Enable Enable at ReadyToBootFsp()
+ 0:Disable, 1:Enable at ReadyToBootFsp()
**/
UINT8 PatrolScrubNotify;
-/** Offset 0x024B - Patrol Scrub Interval
+/** Patrol Scrub Interval
Patrol Scrub Interval in FSP.
**/
UINT8 PatrolScrubDuration;
-/** Offset 0x024C - Patrol Scrub Address Mode
- Selects the address mode between <b>1: System Physical Address (Default)</b>, 0:Reverse
- Address in FSP.
+/** Patrol Scrub Address Mode
+ Selects the address mode between <b>System Physical Address (0x1 - Default)</b>
+ or Reverse Address (0x0) in FSP.
0:Reverse Address, 1:System Physical Address
**/
UINT8 PatrolScrubAddrMode;
-/** Offset 0x024D - Memory Thermal Throttling Mode
- Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, <b>2:CLTT_ENABLE(Default)</b>,
- 3:CLTT_PECI_ENABLE.
- 0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE
+/** Memory Thermal Throttling Mode
+ Memory Configure Memory Thermal Throttling Mode in FSP.
+ 0:Disable, 2:CLTT, 3:CLTT with PECI
**/
UINT8 thermalthrottlingsupport;
-/** Offset 0x024E - Memory Correctable Error Threshold
+/** Memory Correctable Error Threshold
Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
**/
UINT16 spareErrTh;
-/** Offset 0x0250 - WR CRC feature Control
- Enable/Disable Write CRC in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** WR CRC feature Control
+ Enable/Disable Write CRC in FSP.
+ $EN_DIS
**/
UINT8 WrCRC;
-/** Offset 0x0251 - Adaptive Refresh Management Level
+/** DDR 2x Refresh Enable
+ Enable/Disable 2x Refresh. Auto = dynamically selected.
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 RefreshMode;
+
+/** Adaptive Refresh Management Level
Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
- required. <b>0:Default - RAAIMT, RAAMMT, RAADEC(Default)</b>; 1:Level A - RAAIMT-A,
- RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C,
- RAAMMT-C, RAADEC-C
- 0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level
- B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C
+ required. 0:Default - RAAIMT, RAAMMT, RAADEC; 1:Level A - RAAIMT-A, RAAMMT-A, RAADEC-A;
+ 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, RAAMMT-C, RAADEC-C
+ 0:Default - RAAIMT or RAAMMT or RAADEC, 1:Level A - RAAIMT-A or RAAMMT-A or RAADEC-A,
+ 2:Level B - RAAIMT-B or RAAMMT-B or RAADEC-B, 3:Level C - RAAIMT-C or RAAMMT-C
+ or RAADEC-C
**/
UINT8 AdaptiveRefreshMgmtLevel;
-/** Offset 0x0252 - MEMHOT INPUT Control
- Enable/Disable MEMHOT INPUT in FSP - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** CXL Hetero Support
+ Enable/Disable (Default) DDR CXL Heterogeneous Interleave in FSP.
+ $EN_DIS
**/
- UINT8 MemHotIn;
+ UINT8 CxlHeteroSupport;
-/** Offset 0x0253 - MEMHOT OUTPUT Mode
- MEMHOT OUTPUT Mode in FSP - 0:Disable, <b>1:Enable only temphi(Default)</b>, 2:Enable
- temphi & mid, 3:Enable temphi & mid & low.
- 0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low
+/** MEMHOT INPUT Control
+ Enable/Disable MEMHOT INPUT in FSP.
+ $EN_DIS
**/
- UINT8 MemhotOutputOnlyOpt;
+ UINT8 MemHotIn;
-/** Offset 0x0254 - CxlType3LegacyEn
- Enable or disable CXL type 3 device using CXL type 2 flow - <b>0:Disable(Default)</b>, 1:Enable.
- 0:Disable, 1:Enable
+/** MEMHOT OUTPUT Mode
+ MEMHOT OUTPUT Mode in FSP.
+ 0:Disable, 1:Enable only temphi, 2:Enable only temphi and mid, 3:Enable only temphi
+ mid and low
**/
- UINT8 DfxCxlType3LegacyEn;
+ UINT8 MemhotOutputOnlyOpt;
-/** Offset 0x0255 - DfxPmicSecureMode
- 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, <b>2:Auto Pmic Secure Mode(Default)</b>.
+/** DfxPmicSecureMode
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode.
0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
**/
UINT8 DfxPmicSecureMode;
-/** Offset 0x0256 - IIO PcieSubSystemMode0
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode0[8];
-
-/** Offset 0x025E - IIO PcieSubSystemMode1
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode1[8];
-
-/** Offset 0x0266 - IIO PcieSubSystemMode2
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+/** SpdPrintEn
+ Enable/Disable SPD Print
+ $EN_DIS
**/
- UINT8 IioPcieSubSystemMode2[8];
+ UINT8 SpdPrintEn;
-/** Offset 0x026E - IIO PcieSubSystemMode3
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode3[8];
-
-/** Offset 0x0276 - IIO PcieSubSystemMode4
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode4[8];
-
-/** Offset 0x027E - IIO PcieSubSystemMode5
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
-**/
- UINT8 IioPcieSubSystemMode5[8];
-
-/** Offset 0x0286 - IIO PcieSubSystemMode6
- PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
- 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+/** Force PPR On All Dram For UCE
+ Enable/Disable force PPR on all dram for UCE.
+ 0:Disable, 1:Enable
**/
- UINT8 IioPcieSubSystemMode6[8];
+ UINT8 ForcePprOnAllDramUce;
-/** Offset 0x028E - CXL Header Bypass
- Enable/Disable the CXL header bypass in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
+/** CXL Header Bypass
+ Enable/Disable the CXL header bypass in FSP.
0:Disable, 1:Enable
**/
UINT8 DfxCxlHeaderBypass;
-/** Offset 0x028F - CXL Security Level
+/** CXL Security Level
CXL Security Level<br>\n
- 0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
+ 0- Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
attached memory ranges in the WB address space.<br>\n
- 1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
+ 1- Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
ranges only;<br>\n
- 2: Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
- <b>3: Auto - Currently identical to Fully Trusted. (Default)</b>
+ 2- Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
+ <b>3- Auto - Currently identical to Fully Trusted. (Default)</b>
0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
**/
UINT8 DfxCxlSecLvl;
-/** Offset 0x0290
-**/
- UINT32 DfxCxlDebugModePtr;
-
-/** Offset 0x0294
-**/
- UINT32 DfxCxlDebugModeNumber;
-
-/** Offset 0x0298 - Lock Chipset
- Lock or Unlock chipset in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** CXL VID
+ CXL VID on SPR B0. Auto(Default) and Enable is 0x1E98. Disable is 0x8086
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 LockChipset;
+ UINT8 DfxCxlVid;
-/** Offset 0x0299 - MSR Lock Control
- Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
- remove lock bits - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** Warm-Reset Elimination
+ When enabled, BIOS will attempt to skip warm-reset on the cold-reset path. Auto:
+ platform or silicon RC policy determines feature status
+ 0:Disable, 1:Enable, 2:Auto
**/
- UINT8 ProcessorMsrLockControl;
+ UINT8 DfxWarmResetEliminationEn;
-/** Offset 0x029A - DFX Enable
- When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - <b>0:Disabled(Default)</b>,
- 1:Enabled.
- 0:Disable, 1:Enable
+/** IIO DFX CxlDebugMode Ptr
+ Pointer to array of CxlDebugMode settings Per Port, 0x00000000 indicates Dfx CXL
+ Debug mode Disable.
**/
- UINT8 DFXEnable;
+ UINT32 DfxCxlDebugModePtr;
-/** Offset 0x029B - DFX Disable Bios Done
- When Enabled, suppresses notifying processor via MSR 151h that boot initialization
- is finished in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
- 0:Disable, 1:Enable
+/** IIO DFX CxlDebugMode Number
+ Number of elements in DfxCxlDebugModePtr array, port number as unit, should be set
+ along with DfxCxlDebugModePtr.
**/
- UINT8 DfxDisableBiosDone;
+ UINT32 DfxCxlDebugModeNumber;
-/** Offset 0x029C - Processor Package C State
- Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
+/** Processor Package C State
+ Package C State 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
state, 7: No Limit, <b>0xFF: Auto (Default)</b>
0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
7: No Limit, 0xFF: Auto
**/
UINT8 CpuPmPackageCState;
-/** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech
- Enhanced Intel SpeedStep(R) Tech - <b>1: Enable(Default)</b>, 0: Disable.
- 0:Disabled, 1:Enabled
+/** Enhanced Intel SpeedStep(R) Tech
+ Enable(Default)/Disable Enhanced Intel SpeedStep(R) Tech
+ $EN_DIS
**/
UINT8 CpuPmEistEnable;
-/** Offset 0x029E - C1E
- C1E - <b>1: Enable(Default)</b>, 0: Disable.
+/** C1E
+ Enable(Default)/Disable C1E
+ $EN_DIS
**/
UINT8 CpuPmC1eEnable;
-/** Offset 0x029F - Intel SST-PP
- Intel SST-PP Select allows user to choose level - <b>0xFF: Choose lowest level hardware
- supported(Default)</b>, 0: Level 0, 3: Level 3, 4: Level 4.
+/** Intel SST-PP
+ Intel SST-PP Select allows user to choose level.\n
+ AUTO: Choose lowest level hardware supported.
+ 0xFF: AUTO (default), 0: Level 0, 1: Level 1, 2: Level 2, 3: Level 3, 4: Level 4
**/
- UINT8 CpuPmIssTdpLevel;
+ UINT8 CpuPmSstPpLevel;
-/** Offset 0x02A0 - Activate SST-BF
+/** Intel SST-BF
SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
- 0:Disabled, 1:Enabled
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorSstBfSetting;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die0;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die1;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die2;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die0;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die1;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die2;
+
+/** Processor Dynamic Intel Speed Select (ISS) Function
+ Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function
+ $EN_DIS
+**/
+ UINT8 CpuPmDynamicIss;
+
+/** BIOS Region Base
+ Pointer to the location of the BIOS Region
**/
- UINT8 CpuPmProcessorActivePbf;
+ UINT32 BiosRegionBase;
-/** Offset 0x02A1
+/** BIOS Region Size
+ The size of the BIOS Region in bytes
**/
- UINT8 UnusedUpdSpace13[7];
+ UINT32 BiosRegionSize;
-/** Offset 0x02A8 - Socket 0 Core Disable Bitmask
- Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core
- disabled by user will force static SST-PP.
+/** Platform Data Area Base
+ Pointer to the location of the Platform Data Area
**/
- UINT64 CpuPmCoreDisableBitmask0;
+ UINT32 PlatformDataAreaBase;
-/** Offset 0x02B0 - Socket 1 Core Disable Bitmask
- Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core
- disabled by user will force static SST-PP.
+/** Platform Data Area Size
+ The size of the Platform Data Area in bytes
**/
- UINT64 CpuPmCoreDisableBitmask1;
+ UINT32 PlatformDataAreaSize;
-/** Offset 0x02B8
+/** N/A
**/
UINT8 ReservedMemoryInitUpd[16];
-/** IIO Board settings Hob Ptr
- Pointer to array of IIO_BOARD_SETTINGS_HOB
+/** Enable TME
+ Enable TME
+ $EN_DIS
**/
- UINT32 IioBoardSettingsHobPtr;
+ UINT8 SecurityCctEnableTme;
-/** IIO Board Settings Hob length
- The IIO Board Settings Hob Length.
+/** Enable TME CR
+ Enable TME CR
+ $EN_DIS
**/
- UINT32 IioBoardSettingsHobLength;
+ UINT8 SecurityCctEnableTmeCR;
-/** BIOS Region Base
- Pointer to the location of the BIOS Region
+/** Enable MKTME
+ Enable MKTME
+ $EN_DIS
**/
- UINT32 BiosRegionBase;
-
-/** BIOS Region Size
- The size of the BIOS Region in bytes
+ UINT8 SecurityCctEnableMktme;
+
+/** Enable Global Integrity
+ Enable Global Integrity
+ $EN_DIS
**/
- UINT32 BiosRegionSize;
+ UINT8 SecurityCctEnableGlobalIntegrity;
+
+/** Select TME Crypto Algorithm
+ Enable Global Integrity
+ 0:Algo1,1:Algo2, 2:Algo3
+**/
+ UINT16 SecurityCctTmeCryptoAlg;
+
+/** Enable TDX
+ : Enable TDX
+**/
+ UINT8 SecurityCctEnableTdx;
+
+/** Enable TDX Connect
+ : Enable TDX Connect
+**/
+ UINT8 SecurityCctEnableTdxConnect;
+
+/** TDX Physical PCIe Port Disable Bitmap
+ TDX Physical PCIe Port Disable Bitmap
+**/
+ UINT16 SecurityCctTdxPhysicalPciePortDisableBitmap[8];
+
+/** Key Split
+ : Key Split
+**/
+ UINT8 SecurityCctKeySplit;
+
+/** Enable TDX SEAM Loader
+ : Enable TDX SEAM Loader
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxSeamldr;
+
+/** Enabne SGX
+ : Enable SGX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSgx;
+
+/** Dfx Sgx CMCS Payload
+ Dfx Sgx CMCS Payload
+**/
+ UINT64 SecurityCctDfxSgxCmcsPayload[16];
+
+/** SGX QoS
+ : SGX QoS
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxQoS;
+
+/** SGX Auto Registration Agent
+ : SGX Auto Registration Agent
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxAutoRegistrationAgent;
+
+/** SGX Package Info In Band Access
+ : SGX Package Info In Band Access
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxPackageInfoInBandAccess;
+
+/** EPOCH Update
+ : EPOCH Update
+ 3:EpochDeactived, 0:EpochActived, 1:NewRandomEpoch, 2:ManualEpoch
+**/
+ UINT8 SecurityCctEpochUpdate;
+
+/** SGX EPOCH 0
+ : SGX EPOCH 0
+**/
+ UINT64 SecurityCctSgxEpoch0;
+
+/** SGX EPOCH 1
+ : SGX EPOCH 1
+**/
+ UINT64 SecurityCctSgxEpoch1;
+
+/** SGX LeWr
+ : SGX LeWr
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxLeWr;
+
+/** SGX Le Public Key Hash 0
+ : SGX Le Public Key Hash 0
+**/
+ UINT64 SecurityCctSgxLePubKeyHash0;
+
+/** SGX Le Public Key Hash 1
+ : SGX Le Public Key Hash 1
+**/
+ UINT64 SecurityCctSgxLePubKeyHash1;
+
+/** SGX Le Public Key Hash 2
+ : SGX Le Public Key Hash 2
+**/
+ UINT64 SecurityCctSgxLePubKeyHash2;
+
+/** SGX Le Public Key Hash 3
+ : SGX Le Public Key Hash 3
+**/
+ UINT64 SecurityCctSgxLePubKeyHash3;
+
+/** SGX Debug Mode
+ : SGX Debug Mode
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxDebugMode;
+
+/** SGX Factory Reset
+ : SGX Factory Reset
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxFactoryReset;
+
+/** Dfx Bios Param Header Override
+ : Dfx Bios Param Header Override
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxBiosParamHeaderOverride;
+
+/** Dfx Bios Param Header Version
+ : Dfx Bios Param Header Version
+**/
+ UINT16 SecurityCctDfxBiosParamHeaderVersion;
+
+/** Dfx Disable Actm Launch
+ : Dfx Disable Actm Launch
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxDisableActmLaunch;
+
+/** ACTM Flash Base
+ : ACTM Flash Base
+**/
+ UINT32 SecurityCctActmPcdFlash;
+
+/** Enable UPI FLE
+ : Enable UPI FLE
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableUpiFle;
+
+/** Enable SAF
+ : Enable SAF
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSaf;
+
+/** Dfx TDX Disable 1MB CMR Exclude
+ : Dfx TDX Disable 1MB CMR Exclude
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxTdxDisable1MbCmrExclude;
+
+/** Dfx Seamldr Source location
+ : Dfx Seamldr Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxSeamldrSrc;
+
+/** Dfx Tdx module Source location
+ : Dfx Tdx module Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxTdxModuleSrc;
+
+/** Dfx PRMRR SEAMRR Support
+ : Dfx PRMRR SEAMRR Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxPrmrrSeamrrSupport;
+
+/** Dfx Simics Environment
+ : Dfx Simics Environment
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSimicsEnvironment;
+
+/** Dfx Force UPL Unsupported
+ : Dfx Force UPL Unsupported
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxForceUplUnsupported;
+
+/** Dfx TME Key Restore
+ : Dfx TME Key Restore
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxTmeKeyRestore;
+
+/** Dfx TME Exclusion Base
+ : Dfx TME Exclusion Base
+**/
+ UINT64 SecurityCctDfxTmeExclusionBase;
+
+/** Dfx TME Exclusion Length
+ : Dfx TME Exclusion Length
+**/
+ UINT64 SecurityCctDfxTmeExclusionLength;
+
+/** Dfx MKTME KeyIdBits Override
+ : Dfx MKTME KeyIdBits Override
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverride;
+
+/** Dfx MKTME KeyIdBits Override Value
+ : Dfx MKTME KeyIdBits Override Value
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverrideValue;
+
+/** Dfx SGX Debug Print
+ : Dfx SGX Debug Print
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxDebugPrint;
+
+/** Dfx SGX Registration Server Select
+ : Dfx SGX Registration Server Select
+ 1:PRX, 0:SBX, 3:LIV, 4:SoftwareDefined, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxRegistrationServerSelect;
+
+/** Dfx SGX Add Package Support
+ : Dfx SGX Add Package Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxAddPackageSupport;
+
+/** Dfx allow SGX non POR memory population
+ : Dfx SGX Add Package Support
+ 1:Enabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxAllowSgxNonPorMemoryPopulation;
+
+/** Dfx SGX Hang Before ACTM
+ : Dfx SGX Hang Before ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeActm;
+
+/** Dfx SGX Hang After ACTM
+ : Dfx SGX Hang After ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterActm;
+
+/** Dfx SGX Hang Before MCHECK
+ : Dfx SGX Hang Before MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMcheck;
+
+/** Dfx SGX Hang After MCHECK
+ : Dfx SGX Hang After MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMcheck;
+
+/** Dfx SGX Hang Before MSR 7A
+ : Dfx SGX Hang Before MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMsr7a;
+
+/** Dfx SGX Hang After MSR 7A
+ : Dfx SGX Hang After MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMsr7a;
+
+/** Dfx disable CCT MSR_BIOS_DONE
+ : Dfx disable CCT MSR_BIOS_DONE
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxDisableCctBiosDone;
+
+/** Dfx Mcheck MSR 72
+ : Dfx Mcheck MSR 72 programming
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMcheckMsr72;
+
+/** Dfx Skip Warm Reset Promotion
+ : Dfx Skip Warm Reset Promotion
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSkipWarmResetPromotion;
+
+/** Enable SBFT
+ : Enable SBFT
+ 1:Enabled, 0:Disabled, 4:IfsSbftSgxEnabled
+**/
+ UINT8 SecurityCctEnableSbft;
+
+/** PRMRR SGX Size
+ : PRMRR SGX Size
+ 0x8000000:128MB, 0x10000000:256MB, 0x20000000:512MB, 0x40000000:1GB, 0x80000000:2GB,
+ 0x100000000:4GB, 0x200000000:8GB,0x400000000:16GB, 0x800000000:32GB, 0x1000000000:64GB,
+ 0x2000000000:128GB, 0x4000000000:256GB, 0x8000000000:512GB
+**/
+ UINT64 SecurityCctPrmrrSgxSize;
+
+/** PRMRR SAF Size
+ : PRMRR SAF Size
+ 0x0:Invalid, 0x800000:8MB, 0x2000000:32MB, 0x4000000:64MB, 0x8000000:128MB, 0x10000000:256MB
+**/
+ UINT64 SecurityCctPrmrrSafSize;
+
+/** PRMRR SBFT Size
+ : PRMRR SBFT Size
+ 0x0:Invalid, 0x10000000:256MB, 0x20000000:512MB
+**/
+ UINT64 SecurityCctPrmrrSbftSize;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** SINIT ACM SE SVN default
+ Default value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnFspDefault;
+
+/** SINIT ACM SE SVN override request
+ Override request for SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnOverrideRequest;
+
+/** SINIT ACM SE SVN value
+ Value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnValue;
+
+/** Setup data pointer
+ : Setup data pointer
+**/
+ UINT64 SetupDataPtr;
+
+/** Setup data Size
+ : Setup data Size
+**/
+ UINT64 SetupDataSize;
+
+/** Emulation Setting data pointer
+ : Emulation Setting data pointer
+**/
+ UINT64 EmulationSettingPtr;
+
+/** Emulation Setting data Size
+ : Emulation Setting data Size
+**/
+ UINT64 EmulationSettingSize;
+
+/** Platform info data pointer
+ : Platform info data pointer
+**/
+ UINT64 PlatformInfoPtr;
+
+/** Platform info data Size
+ : Platform info data Size
+**/
+ UINT64 PlatformInfoSize;
+
+/** FSPM Upd settings support
+ : FSPM Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspmUpdSupport;
+
+/** Gen4 RCD Dimm support
+ Gen4 RCD Dimm support, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen4RcdDeviceSupport;
} FSPM_CONFIG;
+
typedef struct {
-
+
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
/** N/A
**/
FSPM_ARCH2_UPD FspmArchUpd;
-
+
/** N/A
**/
FSPM_CONFIG FspmConfig;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h
index 864a5a983f..11628ff7ee 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -30,261 +30,224 @@ are permitted provided that the following conditions are met:
**/
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
+#ifndef __FSPS_UPD_H__
+#define __FSPS_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
-
-/** FSP-S Configuration
-**/
typedef struct {
-/** Offset 0x0020 - Processor VmxEnable Function
- Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
- 0: Disable, 1: Enable
+/** PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
**/
- UINT8 VmxEnable;
+ UINT8 EnablePcie0;
-/** Offset 0x0021 - Processor TurboMode Function
- Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
- 0: Disable, 1: Enable
+/** PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
**/
- UINT8 TurboMode;
+ UINT8 EnablePcie1;
-/** Offset 0x0022 - Processor Safer Mode Extensions Function
- Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
- Processor Safer Mode Extensions Function.
- 0: Disable, 1: Enable
+/** Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
**/
- UINT8 ProcessorSmxEnable;
+ UINT8 EnableEmmc;
-/** Offset 0x0023 - SstCp
- SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
- 0: Disable, 1: Enable
+/** LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
- UINT8 SstCpSetting;
+ UINT8 EnableGbE;
-/** Offset 0x0024 - SstCp Capable Status
- SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
- 0: Disable, 1: Enable
+/** PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 SstCpCapableSystem;
+ UINT8 PcieRootPort0DeEmphasis;
-/** Offset 0x0025
+/** PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 UnusedUpdSpace0[1];
+ UINT8 PcieRootPort1DeEmphasis;
-/** Offset 0x0026 - PCH Protect Range Limit
- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
- limit comparison.
+/** PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT16 PchProtectedRangeLimit[5];
-
-/** Offset 0x0030 - PCH Protect Range Base
- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
- UINT16 PchProtectedRangeBase[5];
+ UINT8 PcieRootPort2DeEmphasis;
-/** Offset 0x003A - PchAdrEn
- PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
- 0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
+/** PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 PchAdrEn;
+ UINT8 PcieRootPort3DeEmphasis;
-/** FSP smm init enable
- Enable / Disable FSP smm init
- $EN_DIS
+/** PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 FspSmmInitEn;
+ UINT8 PcieRootPort4DeEmphasis;
-/** Offset 0x003B - EnableTme
- EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
- 0: Disabled, 1: Enabled, 2:Software Controlled
+/** PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 EnableTme;
+ UINT8 PcieRootPort5DeEmphasis;
-/** Offset 0x003C - EnableTmeBypass
- EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 EnableTmeBypass;
+ UINT8 PcieRootPort6DeEmphasis;
-/** Offset 0x003D - SgxFactoryReset
- SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
**/
- UINT8 SgxFactoryReset;
+ UINT8 PcieRootPort7DeEmphasis;
-/** Offset 0x003E - EnableSgx
- EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** eMMC DLL Configuration Data
+ Pointer to eMMC DLL Configuration Data
**/
- UINT8 EnableSgx;
+ UINT32 EMMCDLLConfigPtr;
-/** Offset 0x003F - SgxPackageInfoInBandAccess
- SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
**/
- UINT8 SgxPackageInfoInBandAccess;
+ UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x0040 - SgxQoS
- SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
- 0: Disabled, 1: Enabled
+/** PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
- UINT8 SgxQoS;
+ UINT16 PchProtectedRangeBase[5];
-/** Offset 0x0041 - EpochUpdate
- EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
- EPOCHs(Default)</b>.
- 1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
+/** PchAdrEn
+ PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
+ 0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
**/
- UINT8 EpochUpdate;
+ UINT8 PchAdrEn;
-/** Offset 0x0042 - SgxLeWr
- SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** Enable Timed GPIO0
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
**/
- UINT8 SgxLeWr;
+ UINT8 EnableTimedGpio0;
-/** Offset 0x0043 - SgxDebugMode
- SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** Enable Timed GPIO1
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
**/
- UINT8 SgxDebugMode;
+ UINT8 EnableTimedGpio1;
-/** Offset 0x0044 - SgxAutoRegistrationAgent
- SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
- 0: Disabled, 1: Enabled
+/** FSP smm init enable
+ Enable / Disable FSP smm init
+ $EN_DIS
**/
- UINT8 SgxAutoRegistrationAgent;
+ UINT8 FspSmmInitEn;
-/** Offset 0x0045 - DfxSgxRegistrationServerSelect
- DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
- 4:SW Defined Server.
- 0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
+/** C2C3TT
+ Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
+ 0: Default, Bit[11:0] : C2 to C3 Transition Timer
**/
- UINT8 DfxSgxRegistrationServerSelect;
+ UINT8 CpuPmC2c3tt;
-/** Offset 0x0046 - Processor Enable Monitor MWAIT
- Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
- Monitor MWAIT.
- 0: Disabled, 1: Enabled
+/** Processor Enable Monitor MWAIT
+ Enable(Default) or Disable Processor Monitor MWAIT
+ $EN_DIS
**/
UINT8 CpuPmMonitorMWait;
-/** Offset 0x0047 - Processor C6
- Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
- 0: Disabled, 1: Enabled
+/** Processor TurboMode Function
+ Enable(Default) or Disable Processor TurboMode Function
+ $EN_DIS
**/
- UINT8 CpuPmC6Enable;
+ UINT8 CpuPmTurboMode;
-/** Offset 0x0048 - Hardware P-States
- Hardware P-States - 0: Disable: Hardware chooses a P-state based on OS Request
- (Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
- 2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
- Mode with No Legacy Support.
- 0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
+/** Hardware P-States
+ Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
+ Native Mode:Hardware chooses a P-state based on OS guidance\n
+ Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
+ 0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
**/
UINT8 CpuPmProcessorHWPMEnable;
-/** Offset 0x0049 - Power Performance Tuning
- Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
- EPB, 2: PECI Controls EPB.
- 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
-**/
- UINT8 CpuPmPwrPerfTuning;
-
-/** Offset 0x004A - Configure SST-BF
- Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
- does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
- 0:Disable, 1:Enable
-**/
- UINT8 CpuPmProcessorConfigurePbf;
-
-/** Offset 0x004B - CF9 Global Reset Promotion
- CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
- promoting CF9 reset to global(Default)</b>.
- 0: Disabled, 1: Enabled
-**/
- UINT8 MeGrPromotionEnabled;
-
-/** Offset 0x004C - Global Reset Lock
- Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
- 0: Disable locking the joint ME and host reset capability.
- 0: Disabled, 1: Enabled
-**/
- UINT8 MeGrLockEnabled;
-
-/** Offset 0x004D - Delayed Authentication Mode
- Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
- 0:Disable, 1:Enable
+/** HardwarePM Interrupt
+ Enable or Disable (Default) Hardware PM Interrupt
+ $EN_DIS
**/
- UINT8 DelayedAuthenticationMode;
+ UINT8 CpuPmProcessorHWPMInterrupt;
-/** Offset 0x004E - Delayed Authentication Mode Override
- Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+/** EPP Profile
+ Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
+ Power, 255: Power
+ 0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
**/
- UINT8 DelayedAuthenticationModeOverride;
+ UINT8 CpuPmProcessorEPPProfile;
-/** Offset 0x004F - Core Bios Done Message
- Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Boot Performance Mode
+ Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
+ 1: Max Efficiency
+ 0: Max Performance (Default), 1: Max Efficiency
**/
- UINT8 CoreBiosDoneEnabled;
+ UINT8 CpuPmBootPstate;
-/** Offset 0x0050 - End Of Post Message
- Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
- <b>2: Send in DXE(Default)</b>.
- 0:Disable, 1:Send in PEI, 2:Send in DXE
+/** Power Performance Tuning
+ Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
+ 2: PECI Controls EPB
+ 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
**/
- UINT8 EndOfPostMessage;
+ UINT8 CpuPmPwrPerfTuning;
-/** Offset 0x0051 - HMRFPO_LOCK Message
- Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
- 0:Disable, 1:Enable
+/** Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor, 0: Disable, 1: Enable
+ $EN_DIS
**/
- UINT8 MeHmrfpoLockEnabled;
+ UINT8 ThermalMonitor;
-/** Offset 0x0052 - HMRFPO_ENABLE Message
- Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
- 1: Enable.
- 0:Disable, 1:Enable
+/** FSPS Upd settings support
+ : FSPS Upd settings support
+ $EN_DIS
**/
- UINT8 MeHmrfpoEnableEnabled;
+ UINT8 FspsUpdSupport;
-/** Offset 0x0053
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
**/
- UINT8 UnusedUpdSpace1[1];
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
-/** Offset 0x0054
+/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
+
} FSPS_CONFIG;
-/** Fsp S UPD Configuration
-**/
+
typedef struct {
-/** Offset 0x0000
+/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-/** Offset 0x0020
+/** N/A
**/
- FSPS_CONFIG FspsConfig;
+ FSPS_ARCH2_UPD FspsArchUpd;
-/** Offset 0x0064
+/** N/A
**/
- UINT8 UnusedUpdSpace2[2];
+ FSPS_CONFIG FspsConfig;
-/** Offset 0x0066
+/** N/A
**/
UINT16 UpdTerminator;
+
} FSPS_UPD;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h
index 77ed502735..2e7cfa164c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -38,19 +38,19 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
typedef struct {
-
+
/** N/A
**/
UINT64 MicrocodeRegionBase;
-
+
/** N/A
**/
UINT64 MicrocodeRegionLength;
-
+
/** N/A
**/
UINT64 CodeRegionBase;
-
+
/** N/A
**/
UINT64 CodeRegionLength;
@@ -60,13 +60,11 @@ typedef struct {
typedef struct {
-/** Offset 0x0040 - Disable Port80 output in FSP-T
- Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
- 2:Disable Port80 Output, refer to FSP Integration Guide for details.
+/** Disable Port80 output in FSP-T
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
**/
UINT8 FsptPort80RouteDisable;
-
+
/** N/A
**/
UINT8 ReservedTempRamInitUpd[31];
@@ -75,23 +73,23 @@ typedef struct {
typedef struct {
-
+
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
-
+
/** N/A
**/
FSPT_ARCH2_UPD FsptArchUpd;
-
+
/** N/A
**/
FSPT_CORE_UPD FsptCoreUpd;
-
+
/** N/A
**/
FSPT_CONFIG FsptConfig;
-
+
/** N/A
**/
UINT16 UpdTerminator;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
index 53dd0ea75b..27633c7462 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,35 +26,90 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _IIO_PCIE_CONFIG_UPD_H_
#define _IIO_PCIE_CONFIG_UPD_H_
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_LOGIC_IIO_STACK
-#define MAX_LOGIC_IIO_STACK 14
+#define MAX_LOGIC_IIO_STACK 18
#endif
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET 57
+/**
+ * Maximum number of IIO ports per IIO stack.
+ */
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK 8
#endif
-#ifndef MAX_IOU_PER_SOCKET
-#define MAX_IOU_PER_SOCKET 7
-#endif
+#define MAX_IIO_STACK 16
+#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
+#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
-#ifndef MAX_IIO_PORTS_PER_STACK
-#define MAX_IIO_PORTS_PER_STACK 1
+#if MAX_SOCKET <= 4
+
+//
+// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
+// However, we share R1S image with 4 socket SP image, no separate build for R1S.
+// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
+//
+#define MAX_IIO_PCIE_PER_SOCKET 10
+#else
+#define MAX_IIO_PCIE_PER_SOCKET 6
#endif
+#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
+
+#define IIO_BIFURCATE_xxxxxxxx 0xFE
+#define IIO_BIFURCATE_x4x4x4x4 0x0
+#define IIO_BIFURCATE_x4x4xxx8 0x1
+#define IIO_BIFURCATE_xxx8x4x4 0x2
+#define IIO_BIFURCATE_xxx8xxx8 0x3
+#define IIO_BIFURCATE_xxxxxx16 0x4
+#define IIO_BIFURCATE_x2x2x4x8 0x5
+#define IIO_BIFURCATE_x4x2x2x8 0x6
+#define IIO_BIFURCATE_x8x2x2x4 0x7
+#define IIO_BIFURCATE_x8x4x2x2 0x8
+#define IIO_BIFURCATE_x2x2x4x4x4 0x9
+#define IIO_BIFURCATE_x4x2x2x4x4 0xA
+#define IIO_BIFURCATE_x4x4x2x2x4 0xB
+#define IIO_BIFURCATE_x4x4x4x2x2 0xC
+#define IIO_BIFURCATE_x2x2x2x2x8 0xD
+#define IIO_BIFURCATE_x8x2x2x2x2 0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
+
+#define IIO_BIFURCATE_xxxxxxx4 0x40
+#define IIO_BIFURCATE_xxx2xxx2 0x41
+#define IIO_BIFURCATE_x1x1xxx2 0x42
+#define IIO_BIFURCATE_xxx2x1x1 0x43
+#define IIO_BIFURCATE_x1x1x1x1 0x44
+
+#define IIO_BIFURCATE_AUTO 0xFF
-#define MAX_IIO_PCIE_PER_SOCKET 1
+#define C1_UID 2
+#define C2_UID 3
-#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD
+/**
+ * VTBAR - Virtualization Technology BAR region size and alignment.
+ */
+#define IIO_VTBAR_LSB 16 // 64 kB
+#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
#pragma pack(1)
@@ -73,91 +128,6 @@ typedef enum {
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
-typedef struct {
- UINT8 Address; // SMBUS address of IO expander which provides NPEM
- UINT8 Bank; // Port or bank on IoExpander which provides NPEM
- UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
- UINT8 MuxChannel; // Channel of the MUX used to access NPEM
-} IIO_NPEM_CFG;
-
-typedef struct {
- UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
- UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
- UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
- UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
- UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
- UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
- UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
- UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
- UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
- UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
- BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
- UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
- UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
- UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
- UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
-
- UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
- UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu
- UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
- UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
- UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
- UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
- UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
- UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
- UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
- UINT8 PcieGlobalAspm;
- UINT8 PcieMaxReadRequestSize;
-} UPD_IIO_PCIE_PORT_CONFIG;
-
-typedef struct {
- UINT8 Address;
- UINT8 Port;
- UINT8 MuxAddress;
- UINT8 MuxChannel;
-} IIO_VPP_CFG;
-
-typedef struct {
- UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
- UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
- UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
- UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
- UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
- UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
-
- UINT8 Reserved : 2;
-} IIO_SLOT_CFG;
-
-typedef struct {
-
- IIO_VPP_CFG Vpp;
- IIO_NPEM_CFG Npem;
- IIO_SLOT_CFG Slot;
-
- UINT8 VppEnabled :1;
- UINT8 VppExpType :1;
- UINT8 NpemSupported :1;
-
- UINT8 SlotImplemented :1;
- UINT8 Retimer1Present :1;
- UINT8 Retimer2Present :1;
- UINT8 CommonClock :1;
- UINT8 SRIS :1;
-
- UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
- UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
- UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
- UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
-
- UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
-} IIO_BOARD_SETTINGS_PER_PORT;
-
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
@@ -182,7 +152,6 @@ typedef struct {
} PCI_BASE_LIMITS;
typedef struct {
- PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
@@ -211,37 +180,62 @@ typedef struct {
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
-#define IIO_BIFURCATE_xxxxxxxx 0xFE
-#define IIO_BIFURCATE_x4x4x4x4 0x0
-#define IIO_BIFURCATE_x4x4xxx8 0x1
-#define IIO_BIFURCATE_xxx8x4x4 0x2
-#define IIO_BIFURCATE_xxx8xxx8 0x3
-#define IIO_BIFURCATE_xxxxxx16 0x4
-#define IIO_BIFURCATE_x2x2x4x8 0x5
-#define IIO_BIFURCATE_x4x2x2x8 0x6
-#define IIO_BIFURCATE_x8x2x2x4 0x7
-#define IIO_BIFURCATE_x8x4x2x2 0x8
-#define IIO_BIFURCATE_x2x2x4x4x4 0x9
-#define IIO_BIFURCATE_x4x2x2x4x4 0xA
-#define IIO_BIFURCATE_x4x4x2x2x4 0xB
-#define IIO_BIFURCATE_x4x4x4x2x2 0xC
-#define IIO_BIFURCATE_x2x2x2x2x8 0xD
-#define IIO_BIFURCATE_x8x2x2x2x2 0xE
-#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
-#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
-#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
-#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
-#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
-#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
-#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
-#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
-#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
-#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
-#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
-#define IIO_BIFURCATE_AUTO 0xFF
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides VPP register
+ UINT8 Port; // Port or bank on IoExpander which provides VPP register
+ UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
+ UINT8 MuxChannel; // Channel of the MUX used to access VPP
+} IIO_VPP_CFG;
-#define C1_UID 2
-#define C2_UID 3
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides NPEM
+ UINT8 Bank; // Port or bank on IoExpander which provides NPEM
+ UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
+ UINT8 MuxChannel; // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
+ UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+ UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+ UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+ UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+ UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
+ UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+
+ UINT8 Reserved : 2;
+} IIO_SLOT_CFG;
+
+typedef struct {
+ //
+ // Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
+ //
+ IIO_VPP_CFG Vpp;
+ IIO_NPEM_CFG Npem;
+ IIO_SLOT_CFG Slot;
+
+ UINT8 VppEnabled :1; // If VPP is supported on given port
+ UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
+ UINT8 NpemSupported :1; // If NPEM is supported on given port
+
+ //
+ // Below is an excerpt IIO_PCIE_PORT_CONFIG
+ //
+ UINT8 SlotImplemented :1;
+ UINT8 Retimer1Present :1;
+ UINT8 Retimer2Present :1;
+ UINT8 CommonClock :1;
+ UINT8 SRIS :1;
+
+ //
+ // Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
+ //
+ UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
+ UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
+ UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
+ UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
+
+ UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
+} IIO_BOARD_SETTINGS_PER_PORT;
typedef enum {
IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
@@ -271,6 +265,13 @@ typedef enum {
IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
+
+ IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
+ IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
+ IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
+ IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
+ IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
+
IioBifurcation_Auto = IIO_BIFURCATE_AUTO
} IIO_BIFURCATION;
@@ -286,6 +287,9 @@ typedef struct {
IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
} IIO_BOARD_SETTINGS_PER_SOCKET;
+//
+// HOB to store board settings data created based on UBA data
+//
typedef struct {
IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
} IIO_BOARD_SETTINGS_HOB;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
index 6631a39452..cc82d24482 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,107 +26,70 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#define _IIO_UNIVERSAL_DATA_HOB_H_
-#define DINO_UID 0
-#define PC_UID 1
-#define UB_UID 4
-#define CPM0_UID 5
-#define HQM0_UID 6
-
-#define IIO_UNIVERSAL_DATA_GUID { \
- 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
- 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
-}
+#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#if (MAX_SOCKET == 1)
- #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
+ #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#else
- #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
+ #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#endif //(MAX_SOCKET == 1)
-#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
-#endif
-
-#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
-#endif
-
-#ifndef MAX_CH
-#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
-#endif
-
-#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
-
-#ifndef MAX_IIO_PORTS_PER_SOCKET
-#define MAX_IIO_PORTS_PER_SOCKET 57
-#endif
-
-#ifndef MAX_IIO_PORTS_PER_STACK
-#define MAX_IIO_PORTS_PER_STACK 8
-#endif
+#define MAX_LOGIC_IIO_STACK 18
#ifndef MAX_IIO_PCIROOTS_PER_STACK
-#define MAX_IIO_PCIROOTS_PER_STACK 1
+#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
#endif
-#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK 12
-#endif
-
-#define MAX_LOGIC_IIO_STACK 14
-
-#define MAX_COMPUTE_DIE 1
-#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
+#define MAX_COMPUTE_DIE 3
+#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
-#pragma pack(1)
-
-typedef struct _UINT64_STRUCT {
- UINT32 lo;
- UINT32 hi;
-} UINT64_STRUCT, *PUINT64_STRUCT;
-
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
-typedef enum {
- TYPE_SCF_BAR = 0,
- TYPE_PCU_BAR,
- TYPE_MEM_BAR0,
- TYPE_MEM_BAR1,
- TYPE_MEM_BAR2,
- TYPE_MEM_BAR3,
- TYPE_MEM_BAR4,
- TYPE_MEM_BAR5,
- TYPE_MEM_BAR6,
- TYPE_MEM_BAR7,
- TYPE_SBREG_BAR,
- TYPE_MAX_MMIO_BAR
-} MMIO_BARS;
+#ifndef MAX_MESSAGE_LENGTH
+#define MAX_MESSAGE_LENGTH 500
#endif
-typedef struct {
- UINT8 Device;
- UINT8 Function;
-} IIO_PORT_INFO;
+#define DINO_UID 0
+#define PC_UID 1
+#define UB_UID 4
+#define CPM0_UID 5
+#define HQM0_UID 6
-typedef struct {
- UINT8 Major;
- UINT8 Minor;
- UINT8 Revision;
- UINT16 BuildNumber;
-} RC_VERSION;
+typedef enum {
+ IioStack0 = 0,
+ IioStack1 = 1,
+ IioStack2 = 2,
+ IioStack3 = 3,
+ IioStack4 = 4,
+ IioStack5 = 5,
+ IioStack6 = 6,
+ IioStack7 = 7,
+ IioStack8 = 8,
+ IioStack9 = 9,
+ IioStack10 = 10,
+ IioStack11 = 11,
+ IioStack12 = 12,
+ IioStack13 = 13,
+ IioStack14 = 14,
+ IioStack15 = 15,
+ IioStack16 = 16,
+ IioStackUnknown = 0xFF
+} IIO_STACK;
//--------------------------------------------------------------------------------------//
// Structure definitions for Universal Data Store (UDS)
//--------------------------------------------------------------------------------------//
+#pragma pack(1)
+
typedef struct {
UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
UINT8 PeerSocId; // Socket ID
@@ -136,52 +99,16 @@ typedef struct {
typedef struct {
UINT8 Valid;
- UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
UINT8 PcieSegment;
- UINT64_STRUCT SegMmcfgBase;
+ UINT64 SegMmcfgBase;
UINT32 StackPresentBitmap;
- UINT16 CxlPresentBitmap;
- UINT16 Cxl20CapableBitmap;
- UINT8 TotM3Kti;
+ UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
+ UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
UINT8 TotCha;
- UINT32 ChaList[MAX_CHA_MAP];
UINT32 SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;
-typedef struct {
- UINT8 Valid;
- UINT8 SocId;
- QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
-} QPI_IIO_DATA;
-
-typedef struct {
- IIO_PORT_INFO PortInfo[MAX_IIO_PORTS_PER_SOCKET];
-} IIO_DMI_PCIE_INFO;
-
-typedef struct _STACK_RES {
- UINT8 Personality;
- UINT8 BusBase; // Base of Bus configured for this stack
- UINT8 BusLimit; // Limit of Bus configured for this stack
- UINT16 IoBase; // Base of IO configured for this stack
- UINT16 IoLimit; // Limit of IO configured for this stack
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
- UINT8 PciResourceBusBase; // Base of Bus resource available for PCI devices
- UINT8 PciResourceBusLimit; // Limit of Bus resource available for PCI devices
- UINT16 PciResourceIoBase; // Base of IO resource available for PCI devices
- UINT16 PciResourceIoLimit; // Limit of IO resource available for PCI devices
- UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
- UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
- UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
- UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
- UINT32 VtdBarAddress; // NOTE: Obsolete, not used in next gen platforms
-} STACK_RES;
-
/**
* PCI resources that establish one PCI hierarchy for PCI Enumerator.
*/
@@ -197,122 +124,87 @@ typedef struct {
UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
} UDS_PCIROOT_RES;
+/**
+ * This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
+ * One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
+ */
typedef struct {
UINT8 Personality;
UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
+ UINT8 Segment; // Segment for this stack
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
+ UINT8 Reserved[3]; // Reserved for alignment
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
- UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
UINT64 VtbarAddress; // VT-d Base Address
- UINT64 ChbcrBarAddress;
+ UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
+ UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
} UDS_STACK_RES;
+/**
+ * This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
+ // the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
+ */
typedef struct {
UINT8 Valid;
- UINT8 SocketID; // Socket ID of the IIO (0..3)
- UINT8 BusBase;
- UINT8 BusLimit;
+ UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT16 IoBase;
UINT16 IoLimit;
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
+ UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
} UDS_SOCKET_RES;
+/**
+ * This structore keeps resource ranges configured in whole system.
+ */
typedef struct {
- UINT8 Valid;
- UINT8 SocketID; // Socket ID of the IIO (0..3)
- UINT8 BusBase;
- UINT8 BusLimit;
- UINT16 PciResourceIoBase;
- UINT16 PciResourceIoLimit;
- UINT32 IoApicBase;
- UINT32 IoApicLimit;
- UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
- UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
- UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
- UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
- UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
- IIO_DMI_PCIE_INFO PcieInfo; // NOTE: Obsolete, not used in next gen platforms
-} IIO_RESOURCE_INSTANCE;
+ UINT16 SystemIoBase; // System IO Base
+ UINT16 SystemIoLimit; // System IO Limit
+ UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
+ UINT32 SystemIoApicLimit;
+ UINT32 SystemMmio32Base; // System low MMIO base
+ UINT32 SystemMmio32Limit; // System low MMIO limit
+ UINT64 SystemMmio64Base; // System high MMIO Base
+ UINT64 SystemMmio64Limit; // System high MMIO Limit
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ UINT64 PciExpressBase; // PCI Config Space base address
+ UINT64 PciExpressSize; // PCI Config Space size
+ UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
+ UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ UINT16 IoGranularity;
+ UINT32 Mmio32Granularity;
+ UINT64 Mmio64Granularity;
+ UINT32 UboxMmioSize;
+ UINT32 MemTolm;
+ UINT32 MemTsegSize;
+ UINT32 MaxAddressBits;
+} PLATFORM_DATA;
typedef struct {
- UINT16 PlatGlobalIoBase; // Global IO Base
- UINT16 PlatGlobalIoLimit; // Global IO Limit
- UINT32 PlatGlobalMmio32Base; // Global Mmiol base
- UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
- UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
- UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
- QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
- QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
- UINT16 SystemIoBase; // System IO Base
- UINT16 SystemIoLimit; // System IO Limit
- UINT32 SystemMmio32Base; // System low MMIO base
- UINT32 SystemMmio32Limit;
- UINT32 Mmio32Granularity;
- UINT64 SystemMmio64Base; // System high MMIO Base
- UINT64 SystemMmio64Limit; // System high MMIO Limit
- UINT64 Mmio64Granularity;
- UINT32 MemTsegSize;
- UINT64 PciExpressBase;
- UINT32 PciExpressSize;
- UINT32 MemTolm;
- UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
- UINT8 numofIIO;
- UINT8 MaxBusNumber;
- UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
- UINT8 EVMode;
- UINT8 SkuPersonality[MAX_SOCKET];
- UINT16 IoGranularity;
- UINT32 MmiolGranularity;
- UINT64_STRUCT MmiohGranularity;
- UINT8 RemoteRequestThreshold; //5370389
- UINT32 UboxMmioSize;
- UINT32 MaxAddressBits;
-} PLATFORM_DATA;
+ BOOLEAN FailFlag;
+ CHAR16 Message[MAX_MESSAGE_LENGTH];
+} REBALANCE_FAIL_INFO;
typedef struct {
- UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
+ UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
- UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
- UINT8 IsocEnable;
- UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
- UINT8 DmiVc1;
- UINT8 DmiVcm;
- UINT32 CpuPCPSInfo;
- UINT8 cpuSubType;
+ UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 SystemRasType;
- UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
- UINT16 tolmLimit;
- RC_VERSION RcVersion;
- BOOLEAN MsrTraceEnable;
- UINT8 DdrXoverMode; // DDR 2.2 Mode
- // For RAS
- UINT8 bootMode;
- UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
+ UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT8 OutSncEn;
UINT8 OutNumOfCluster;
- UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
- UINT16 LlcSizeReg;
- UINT8 chEnabled[MAX_SOCKET][MAX_CH];
- UINT8 memNode[MC_MAX_NODE];
- UINT8 IoDcMode;
- UINT8 DfxRstCplBitsEn;
UINT8 BitsUsed; //For 5 Level Paging
+ REBALANCE_FAIL_INFO RebalanceFailInfo;
} SYSTEM_STATUS;
typedef struct {
@@ -321,32 +213,7 @@ typedef struct {
UINT32 OemValue;
} IIO_UDS;
-typedef enum {
- //for ICX
- IioStack0 = 0, // DmiAsPcie
- IioStack1 = 1, // IOU0
- IioStack2 = 2, // IOU1
- IioStack3 = 3, // IOU2
- IioStack4 = 4, // IOU3
- IioStack5 = 5, // IOU4
- //for SPR
- IioStack6 = 6, // IOU5
- IioStack7 = 7,
- IioStack8 = 8,
- IioStack9 = 9,
- IioStack10 = 10,
- IioStack11 = 11,
- //for later SOC
- IioStack12 = 12,
- IioStack13 = 13,
- IioStack14 = 14,
- IioStack15 = 15,
- IioStack16 = 16,
- IioStack17 = 17,
- IioStack18 = 18,
- IioStackUnknown = 0xFF
-} IIO_STACK;
-
#pragma pack()
-#endif //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
+#endif // _IIO_UNIVERSAL_DATA_HOB_H_
+
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
index ad3eec3b3d..94a85409cf 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _MEMORY_MAP_DATA_HOB_H_
@@ -34,37 +36,51 @@ are permitted provided that the following conditions are met:
#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
+#define MAX_IMC 8 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
-#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGES
+#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
#endif
-#define MAX_CXL_AMT 0
+#ifndef MAX_CXL_HOST_BRIDGE_WAYS
+#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
+#endif
+
+//
+// Macro definitions for abstracted memory decoding target. The data structure is designed to
+// iterate iMC and CXL host bridge host decoded memory in an unified way.
+// definition for GNRSRF/GNRD/GRR
+//
+#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
+
#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
-#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#endif
#ifndef MAX_SPARE_RANK
-#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
+#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#endif
#ifndef MAX_HBM_IO
-#define MAX_HBM_IO 4
+#define MAX_HBM_IO 4
#endif
#ifndef MAX_DIMM
-#define MAX_DIMM 2 // Max DIMM per channel
+#define MAX_DIMM 2 // Max DIMM per channel
#endif
#ifndef MAX_RANK_DIMM
@@ -72,7 +88,7 @@ are permitted provided that the following conditions are met:
#endif
#ifndef MAX_DRAM_CLUSTERS
-#define MAX_DRAM_CLUSTERS 4
+#define MAX_DRAM_CLUSTERS 6
#endif
#ifndef MAX_SAD_RULES
@@ -83,17 +99,17 @@ are permitted provided that the following conditions are met:
#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
#endif
-#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
+#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
-#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
-#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
+#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
+#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
// NGN
-#define NGN_MAX_SERIALNUMBER_STRLEN 4
-#define NGN_MAX_PARTNUMBER_STRLEN 30
-#define NGN_FW_VER_LEN 4
-#define NGN_LOG_TYPE_NUM 2
-#define NGN_LOG_LEVEL_NUM 2
+#define NGN_MAX_SERIALNUMBER_STRLEN 4
+#define NGN_MAX_PARTNUMBER_STRLEN 30
+#define NGN_FW_VER_LEN 4
+#define NGN_LOG_TYPE_NUM 2
+#define NGN_LOG_LEVEL_NUM 2
/**
* Memory channel index conversion macros.
@@ -115,25 +131,14 @@ are permitted provided that the following conditions are met:
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
-typedef UINT8 CXL_INTLV_SET_KEY;
+typedef UINT8 INTLV_SET_KEY;
-#define FSP_RESERVED1_LEN 77
-#define FSP_RESERVED2_LEN 2174
-#define FSP_RESERVED3_LEN 21
-#define FSP_RESERVED4_LEN 130
-#define FSP_RESERVED5_LEN 10
-#define FSP_RESERVED6_LEN 800
+#define FSP_RESERVED1_LEN 5476
+#define FSP_RESERVED2_LEN 1
+#define FSP_RESERVED3_LEN 220
+#define FSP_RESERVED4_LEN 10
#pragma pack(1)
-typedef enum {
- DIMM_RANK_MAP_OUT_UNKNOWN = 0,
- DIMM_RANK_MAP_OUT_MEM_DECODE,
- DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
- DIMM_RANK_MAP_OUT_RANK_DISABLED,
- DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
- DIMM_RANK_MAP_OUT_MAX
-} DIMM_RANK_MAP_OUT_REASON;
-
struct RankDevice {
UINT8 enabled; // 0 = disabled, 1 = enabled
UINT8 logicalRank; // Logical Rank number (0 - 7)
@@ -154,55 +159,58 @@ typedef struct firmwareRev {
} FIRMWARE_REV;
typedef struct DimmDevice {
- UINT8 Present;
- BOOLEAN Enabled;
- UINT8 DcpmmPresent; // 1 - This is a DCPMM
- UINT8 X4Present;
- UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
- UINT8 NumRanks;
- UINT8 keyByte;
- UINT8 actKeyByte2; // Actual module type reported by SPD
- UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
- UINT8 dimmTs; // Thermal sensor data.
- UINT16 VolCap; // Volatile capacity (AEP DIMM only)
- UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
- UINT16 DimmSize;
- UINT32 NVmemSize;
- UINT16 SPDMMfgId; // Module Mfg Id from SPD
- UINT16 VendorID;
- UINT16 DeviceID;
- UINT16 RevisionID;
- UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
- struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
- UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
- UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
- UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
- struct firmwareRev FirmwareVersion; // Firmware revision
- struct RankDevice rankList[MAX_RANK_DIMM];
- UINT16 InterfaceFormatCode;
- UINT16 SubsystemVendorID;
- UINT16 SubsystemDeviceID;
- UINT16 SubsystemRevisionID;
- UINT16 FisVersion; // Firmware Interface Specification version
- UINT8 DimmSku; // Dimm SKU info
- UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
- UINT16 manufacturingDate; // Date the NVDIMM was manufactured
- INT32 commonTck;
- UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
- BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
- UINT8 CidBitMap; // SubRankPer CS for DIMM device
- UINT16 SPDRegVen; // Register Vendor ID in SPD
- DIMM_RANK_MAP_OUT_REASON MapOutReason;
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DcpmmPresent; // 1 - This is a DCPMM
+ UINT8 X4Present;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MCR NumRanks and NumPackageRanks may differ
+ UINT8 keyByte;
+ UINT8 actKeyByte2; // Actual module type reported by SPD
+ UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
+ UINT8 dimmTs; // Thermal sensor data.
+ UINT16 VolCap; // Volatile capacity (AEP DIMM only)
+ UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
+ UINT16 DimmSize;
+ UINT16 SPDMMfgId; // Module Mfg Id from SPD
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
+ struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
+ UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
+ struct firmwareRev FirmwareVersion; // Firmware revision
+ struct RankDevice rankList[MAX_RANK_DIMM];
+ UINT16 InterfaceFormatCode;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ UINT8 DimmSku; // Dimm SKU info
+ UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
+ UINT16 manufacturingDate; // Date the NVDIMM was manufactured
+ INT32 commonTck;
+ UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+ BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
+ UINT8 CidBitMap; // SubRankPer CS for DIMM device
+ UINT16 SPDRegVen; // Register Vendor ID in SPD
+ UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
+ BOOLEAN DimmChanged;
} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
-struct ChannelDevice {
+typedef struct ChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 NumRanks; // Number of ranks on this channel
UINT8 chFailed;
UINT8 ngnChFailed;
- UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
@@ -210,11 +218,11 @@ struct ChannelDevice {
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
-};
+} CHANNEL_DEVICE;
-struct memcontroller {
+typedef struct memcontroller {
UINT32 MemSize;
-};
+} MEMCONTROLLER;
typedef enum {
MemTypeNone = 0,
@@ -251,8 +259,8 @@ typedef struct SADTable {
UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
- UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
- UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
+ UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
+ UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
BOOLEAN local; // 0 - Remote 1- Local
UINT8 IotEnabled; // To indicate if IOT is enabled
UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
@@ -260,8 +268,9 @@ typedef struct SADTable {
UINT8 tgtGranularity; // Interleave mode for target list
UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
UINT8 HostBridgeGran; // Host bridge interleaving granularity.
+ UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges.
UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
- CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
+ INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
} SAD_TABLE;
typedef struct socket {
@@ -271,10 +280,9 @@ typedef struct socket {
UINT8 imcEnabled[MAX_IMC];
UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
- UINT32 SktMemSize2LM; // Total memory excluded from Limit
SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
- struct memcontroller imc[MAX_IMC];
- struct ChannelDevice ChannelInfo[MAX_CH];
+ MEMCONTROLLER imc[MAX_IMC];
+ CHANNEL_DEVICE ChannelInfo[MAX_CH];
} MEMMAP_SOCKET;
typedef struct {
@@ -287,9 +295,10 @@ typedef struct SystemMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
- UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory
- UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
+ UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} SYSTEM_MEMORY_MAP_ELEMENT;
@@ -300,8 +309,6 @@ typedef struct SystemMemoryMapHob {
// All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
//
UINT8 TotalClusters;
-
- UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
@@ -310,14 +317,9 @@ typedef struct SystemMemoryMapHob {
UINT16 memFreq; // Mem Frequency
UINT16 HbmFreq; // HBM Frequency in MHz.
UINT8 memMode; // 0 - Independent, 1 - Lockstep
- UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
- UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage;
- BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS
- BOOLEAN EkvPresent; // Set if EKV controller on system
- BOOLEAN BwvPresent; // Set if BWV controller on system
- BOOLEAN CwvPresent; // Set if CWV controller on system
UINT8 XMPProfilesSup;
UINT8 XMPCapability;
//
@@ -336,35 +338,20 @@ typedef struct SystemMemoryMapHob {
UINT8 NumChPerMC;
UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
- UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup;
- UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar;
+ UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
+ UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
MEMMAP_SOCKET Socket[MAX_SOCKET];
- UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
-
- UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo;
- UINT8 LatchSystemShutdownState;
- BOOLEAN IsWpqFlushSupported;
- UINT8 EadrSupport;
- UINT8 EadrCacheFlushMode;
- UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
- UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
+ UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
+
+ UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
- BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
- UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
- UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
- UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
- UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
- UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
- UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
- UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
- UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
- UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
+ UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
- UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
+ UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
+ BOOLEAN McrMemFreqRangeEn; // MCR Memory Frequency range enabled.
} SYSTEM_MEMORY_MAP_HOB;
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h
index f1d55542c3..6eeabd3e1b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,13 +26,14 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
#define _PREV_BOOT_ERR_SRC_HOB_H_
-#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
-{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000
diff --git a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h
index b6d88f5c30..9f0987a681 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -26,42 +26,41 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
+ This file is automatically generated. Please do NOT modify !!!
+
**/
#ifndef _SYSTEM_INFO_HOB_H_
#define _SYSTEM_INFO_HOB_H_
-#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
+#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
#ifndef MAX_SOCKET
-#define MAX_SOCKET 4
+#define MAX_SOCKET 2
#endif
#ifndef MAX_IIO_STACK
-#define MAX_IIO_STACK 12
+#define MAX_IIO_STACK 16
#endif
-#define MAX_LOGIC_IIO_STACK 14
+#define MAX_LOGIC_IIO_STACK 18
+#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
+#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#ifndef MAX_IMC
-#define MAX_IMC 4 // Maximum memory controllers per socket
+#define MAX_IMC 8 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
-#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
-#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
-#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
-
#pragma pack(1)
-#ifndef MMIO_BARS_ENUM
-#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
@@ -76,7 +75,6 @@ typedef enum {
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
-#endif
typedef enum {
ReservedMemSs,
@@ -95,7 +93,7 @@ typedef enum BootMode {
// in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
// init and be optimized for speed.
-} BootMode;
+} BOOT_MODE;
//
// This is used to determine what type of die is connected to a UPI link
@@ -163,19 +161,6 @@ typedef struct {
} HPM_VSEC_RESOURCE;
-//
-// Stack id swap information, which includes stack swap flag and the new stack id swap array.
-//
-typedef struct {
- BOOLEAN StackSwapFlag;
- UINT8 StackIdSwapArray[MAX_IIO_STACK];
-} STACKID_SWAP_INFO;
-
-typedef struct {
- UINT64 Cxl1p1RcrbBase;
- BOOLEAN Cxl1p1RcrbValid;
-} CXL_1P1_RCRB;
-
typedef struct {
UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
@@ -188,7 +173,6 @@ typedef struct {
UINT8 segmentSocket[MAX_SOCKET];
UINT8 KtiPortCnt;
UINT32 socketPresentBitMap;
- UINT32 SecondaryNodeBitMap;
UINT32 FpgaPresentBitMap;
UINT32 mmCfgBase;
UINT64 SocketMmCfgBase[MAX_SOCKET];
@@ -220,13 +204,17 @@ typedef struct {
BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
BOOLEAN HbmSku;
- UINT8 HcxType[MAX_SOCKET];
- STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
- CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
UINT8 ChopType; //Compute Die Chop Type
UINT8 MdfInstCount;
+ UINT32 UboxMmioSize;
+ UINT32 UboxScfMmioSize;
+ UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
+ UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
+ UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
} CPU_CSR_ACCESS_VAR;
typedef struct {
@@ -261,7 +249,7 @@ typedef struct {
UINT32 CheckPoint;
UINT8 ResetRequired;
UINT8 Emulation;
- BootMode SysBootMode;
+ BOOT_MODE SysBootMode;
CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
UINT64 CpuFreq;
UINT8 SocketId;
--
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