From 86cb421df68f8c22b3cc27fb9ef45a6633724bb6 Mon Sep 17 00:00:00 2001 From: Thejaswani Putta Date: Fri, 20 Sep 2019 15:13:22 -0700 Subject: mb/google/drallion: Disable GBE in firmware for drallion variants BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch Signed-off-by: Thejaswani Putta Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King Reviewed-by: Bora Guvendik Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index f2367ffa1d..8cb1aa3001 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -417,6 +417,6 @@ chip soc/intel/cannonlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- cgit v1.2.3