From 850925ff000d5c43e4d8cd76af35a8c7f39f6efe Mon Sep 17 00:00:00 2001 From: Dtrain Hsu Date: Thu, 26 May 2022 16:36:52 +0800 Subject: mb/google/brya/var/kinox: Add delay time for BH799BB rtd3 This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/kinox/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 2646b630fa..7aa253635e 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -206,6 +206,8 @@ chip soc/intel/alderlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" register "srcclk_pin" = "1" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end end # BH799BBLN -- cgit v1.2.3