From 842ee24340e1c643701ba04f11620dc7152a091b Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 04:14:03 +0200 Subject: skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174 Reviewed-by: Marvin Evers Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/51nb/x210/devicetree.cb | 1 - src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/intel/saddlebrook/devicetree.cb | 1 - src/mainboard/libretrend/lt1000/devicetree.cb | 1 - src/mainboard/protectli/vault_kbl/devicetree.cb | 1 - src/mainboard/purism/librem_skl/devicetree.cb | 1 - src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 83f8e6e563..17a5f75597 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c6ec0856c3..3a11a84eba 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -71,7 +71,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 6756d83485..d888de4a24 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -17,7 +17,6 @@ chip soc/intel/skylake # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9c4a3661c2..6725a913ca 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 503a491263..6ce7aa4560 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index acff2823c6..be5b6c08b7 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -49,7 +49,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[2]" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index e405114769..8694838632 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -30,7 +30,6 @@ chip soc/intel/skylake }" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms -- cgit v1.2.3