From 83faa5d804d183a26b0fa66b5d55bbe5f3b72c89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 5 Jan 2023 15:39:16 +0200 Subject: mb/google,intel: Use common ChromeEC code for lid shutdown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/google/auron/smihandler.c | 32 ++----------------------------- src/mainboard/google/cyan/smihandler.c | 33 ++------------------------------ src/mainboard/google/link/smihandler.c | 28 ++------------------------- src/mainboard/google/rambi/smihandler.c | 32 ++----------------------------- src/mainboard/google/slippy/smihandler.c | 31 ++---------------------------- src/mainboard/intel/strago/smihandler.c | 33 ++------------------------------ src/soc/intel/baytrail/pmutil.c | 11 +++++++++++ src/soc/intel/braswell/pmutil.c | 11 +++++++++++ src/soc/intel/broadwell/pch/pmutil.c | 11 +++++++++++ src/southbridge/intel/common/pmbase.c | 11 +++++++++++ 10 files changed, 56 insertions(+), 177 deletions(-) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 42ab937f3a..237a2b3c31 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include -#include #include #include #include @@ -14,37 +12,11 @@ #include "ec.h" #include -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); } static void mainboard_disable_gpios(void) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 65daab40ef..8f06cf46aa 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include #include "ec.h" #include #include -#include #include #include #include @@ -20,41 +18,14 @@ #define GPIO_SUS7_WAKE_MASK (1 << 12) #define GPIO_SUS1_WAKE_MASK (1 << 13) -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 0570e2c406..4a9dfb0abf 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -6,41 +6,17 @@ #include #include #include -#include #include -#include /* Include EC functions */ #include #include #include "ec.h" -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); - break; - } - - return cmd; -} - void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 29dc8b29ad..3eb1d1d553 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include #include @@ -16,38 +14,12 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index f02ee403f5..71e97af901 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -10,7 +9,6 @@ #include #include #include -#include /* Include EC functions */ #include @@ -23,36 +21,11 @@ #define GPIO_WLAN_DISABLE_L 46 #define GPIO_LTE_DISABLE_L 59 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - /* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) + chromeec_smi_process_events(); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index f8f7c57c48..a625b62a6a 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include "ec.h" #include #include -#include #include #include @@ -19,41 +17,14 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 -static uint8_t mainboard_smi_ec(void) -{ - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; - - /* Log this event */ - if (cmd) - elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); - outl(pm1_cnt, pmbase + PM1_CNT); - break; - } - - return cmd; -} - /* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (alt_gpio_smi & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0) - ; - } + if (alt_gpio_smi & (1 << EC_SMI_GPI)) + chromeec_smi_process_events(); } void mainboard_smi_sleep(uint8_t slp_typ) diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 93024d9fba..79f95bbf03 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -357,3 +358,13 @@ int platform_is_resuming(void) return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index a880183b82..3efcc7b6de 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -356,3 +357,13 @@ int platform_is_resuming(void) return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 4ba30b4ec6..e310416eaa 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -421,6 +422,16 @@ int platform_is_resuming(void) return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; } +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); +} + /* STM Support */ uint16_t get_pmbase(void) { diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 872d994210..5a339c91f7 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "pmbase.h" @@ -94,6 +95,16 @@ int platform_is_resuming(void) return acpi_get_sleep_type() == ACPI_S3; } +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = read_pmbase32(PM1_CNT); + pm1_cnt |= (0xf << 10); + write_pmbase32(PM1_CNT, pm1_cnt); +} + #define ACPI_SCI_IRQ 9 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) -- cgit v1.2.3