From 83f7baec308cffee0709e38c95e3b4726915e2ea Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Wed, 26 Apr 2017 19:30:41 +0530
Subject: soc/intel/common: Add PCI configuration code for UART

Add PCI configuration code support for intel/common/
block/uart module.

Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 .../intel/common/block/include/intelblocks/uart.h  |  3 ++
 src/soc/intel/common/block/uart/Makefile.inc       |  3 +-
 src/soc/intel/common/block/uart/uart.c             | 37 +++++++++++++++++++++-
 3 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
index ed4c7f0127..b46edd76d7 100644
--- a/src/soc/intel/common/block/include/intelblocks/uart.h
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -17,8 +17,11 @@
 #define SOC_INTEL_COMMON_BLOCK_UART_H
 
 #include <arch/io.h>
+#include <device/device.h>
 
 void uart_common_init(device_t dev, uintptr_t baseaddr,
 		uint32_t clk_m_val, uint32_t clk_n_val);
 
+void pch_uart_read_resources(struct device *dev);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_UART_H */
diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc
index 13f5da880f..0ec5314d66 100644
--- a/src/soc/intel/common/block/uart/Makefile.inc
+++ b/src/soc/intel/common/block/uart/Makefile.inc
@@ -1 +1,2 @@
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
\ No newline at end of file
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
\ No newline at end of file
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 729a31ba1e..8c5e4542f6 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -12,8 +12,10 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/uart.h>
 
@@ -33,3 +35,36 @@ void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
 	/* Set M and N divisor inputs and enable clock */
 	lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
 }
+
+#if ENV_RAMSTAGE
+
+__attribute__((weak)) void pch_uart_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+}
+
+static struct device_operations device_ops = {
+	.read_resources		= &pch_uart_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources		= &pci_dev_enable_resources,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_SPT_UART0,
+	PCI_DEVICE_ID_INTEL_SPT_UART1,
+	PCI_DEVICE_ID_INTEL_SPT_UART2,
+	PCI_DEVICE_ID_INTEL_KBP_H_UART0,
+	PCI_DEVICE_ID_INTEL_KBP_H_UART1,
+	PCI_DEVICE_ID_INTEL_KBP_H_UART2,
+	PCI_DEVICE_ID_INTEL_APL_UART0,
+	PCI_DEVICE_ID_INTEL_APL_UART1,
+	PCI_DEVICE_ID_INTEL_APL_UART2,
+	PCI_DEVICE_ID_INTEL_APL_UART3,
+};
+
+static const struct pci_driver pch_uart __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids,
+};
+#endif /* ENV_RAMSTAGE */
-- 
cgit v1.2.3