From 8355e6e72300d463cae243e1fa1bc4b665bf9fd8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 6 Nov 2021 20:51:58 +0200
Subject: google/beltino,jecht: Refactor ChromeOS GPIOs
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Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/google/beltino/chromeos.c | 18 +++++++++++++-----
 src/mainboard/google/beltino/onboard.h  |  6 ++++++
 src/mainboard/google/jecht/chromeos.c   | 17 ++++++++++++-----
 src/mainboard/google/jecht/onboard.h    |  6 ++++++
 4 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index c51af1ad1a..ce3030daf5 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -8,9 +8,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-
-#define GPIO_SPI_WP	58
-#define GPIO_REC_MODE	12
+#include "onboard.h"
 
 #define FLAG_SPI_WP	0
 #define FLAG_REC_MODE	1
@@ -27,6 +25,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
+static bool raw_write_protect_state(void)
+{
+	return get_gpio(GPIO_SPI_WP);
+}
+
+static bool raw_recovery_mode_switch(void)
+{
+	return !get_gpio(GPIO_REC_MODE);
+}
+
 int get_write_protect_state(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@@ -45,11 +53,11 @@ void init_bootmode_straps(void)
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
 
 	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
-	if (get_gpio(GPIO_SPI_WP))
+	if (raw_write_protect_state())
 		flags |= (1 << FLAG_SPI_WP);
 
 	/* Recovery: GPIO12 = RECOVERY_L, active low */
-	if (!get_gpio(GPIO_REC_MODE))
+	if (raw_recovery_mode_switch())
 		flags |= (1 << FLAG_REC_MODE);
 
 	/* Developer: Virtual */
diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h
index 2cced23900..8bd21ce3d5 100644
--- a/src/mainboard/google/beltino/onboard.h
+++ b/src/mainboard/google/beltino/onboard.h
@@ -16,6 +16,12 @@
 /* WLAN wake is GPIO 10 */
 #define WLAN_WAKE_GPIO		10
 
+/* Recovery: GPIO12 = RECOVERY_L, active low */
+#define GPIO_REC_MODE	12
+
+/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+#define GPIO_SPI_WP	58
+
 /* IT8772F defs */
 #define IT8772F_BASE 0x2e
 #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index ff4cef6a60..807e37fcb2 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -12,9 +12,6 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "onboard.h"
 
-#define GPIO_SPI_WP	58
-#define GPIO_REC_MODE	12
-
 #define FLAG_SPI_WP	0
 #define FLAG_REC_MODE	1
 
@@ -30,6 +27,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
+static bool raw_write_protect_state(void)
+{
+	return get_gpio(GPIO_SPI_WP);
+}
+
+static bool raw_recovery_mode_switch(void)
+{
+	return !get_gpio(GPIO_REC_MODE);
+}
+
 int get_write_protect_state(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@@ -48,11 +55,11 @@ void init_bootmode_straps(void)
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
 
 	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
-	if (get_gpio(GPIO_SPI_WP))
+	if (raw_write_protect_state())
 		flags |= (1 << FLAG_SPI_WP);
 
 	/* Recovery: GPIO12 = RECOVERY_L, active low */
-	if (!get_gpio(GPIO_REC_MODE))
+	if (raw_recovery_mode_switch())
 		flags |= (1 << FLAG_REC_MODE);
 
 	/* Developer: Virtual */
diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h
index 1c37d7228d..a6ba80a7b3 100644
--- a/src/mainboard/google/jecht/onboard.h
+++ b/src/mainboard/google/jecht/onboard.h
@@ -37,4 +37,10 @@ enum {
 #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
 #define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)
 
+/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+#define GPIO_SPI_WP	58
+
+/* Recovery: GPIO12 = RECOVERY_L, active low */
+#define GPIO_REC_MODE	12
+
 #endif
-- 
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