From 831a7ef541055ffeebc3103e82670e0d170b098d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 20:51:50 +0300 Subject: intel/cache_as_ram_ht.inc: Fix include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reference to CACHE_AS_RAM was from the days we had romcc boards using socket_mPGA605. Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15224 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/cpu/intel/socket_LGA775/Makefile.inc | 2 +- src/cpu/intel/socket_mPGA604/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 889b19bd27..af57eda762 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,4 +14,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index df700b7472..4548f3d46d 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading -cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -- cgit v1.2.3