From 8239d076bf461413589303c615682004e613e21b Mon Sep 17 00:00:00 2001 From: Thejaswani Putta Date: Fri, 30 Jul 2021 12:38:37 -0700 Subject: mb/google/brya: Add RTD3 for WWAN Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 6 and provide the reset GPIO / src clk pins. BUG=None BRANCH=None TEST=Build and boot the coreboot image, check if device is enumerated in the lspci list after warm/cold reboot cycles, run suspend cycles and check if WWAN is entering L2 LPM. Signed-off-by: Thejaswani Putta Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Bora Guvendik --- src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 12bff55b68..b8d0b5c173 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -140,6 +140,11 @@ chip soc/intel/alderlake device ref sata on end device ref pcie_rp6 on # Enable WWAN PCIE 6 using clk 5 + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "srcclk_pin" = "5" + device generic 0 on end + end register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, .clk_req = 5, -- cgit v1.2.3