From 7e0078b990b7b498391505fb5c492ff7ed8e54cb Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 31 Jan 2016 11:48:15 -0800 Subject: Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/SoC/soc.html | 89 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 53 +++++++++++++++++++++ Documentation/Intel/fsp1_1.html | 13 ++++++ 3 files changed, 155 insertions(+) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 84206823a9..679e022f64 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -18,6 +18,7 @@
  • Start Booting
  • Early Debug
  • Bootblock
    • +
  • TempRamInit
    • @@ -195,6 +196,94 @@ mv build/coreboot.rom.new build/coreboot.rom +
    +

    TempRamInit

    +

    + Enable the call to TempRamInit in two stages: +

    +
      +
    1. Finding the FSP binary in the read-only CBFS region
      2. +
    2. Call TempRamInit
      3. +
    + + +

    Find FSP Binary

    +

    +Use the following steps to locate the FSP binary: +

    +
      +
    1. Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file +
        +
      1. Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of + src/drivers/intel/fsp1_1/cache_as_ram.inc +
        2. +
      2. Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common + specifically building + util.c +
        3. +
      +
      2. +
    2. Debug the result until port 0x80 outputs +
        +
      1. 0x90: POST_FSP_TEMP_RAM_INIT + - Just before calling + TempRamInit +
        2. +
      2. Alternating 0xba and 0x01 - The FSP image was not found
        3. +
      +
      3. +
    3. Add the FSP binary file to the flash image
      4. +
    4. Set the following Kconfig values: +
        +
      • CONFIG_FSP_LOC to the FSP base address specified in the previous step
        • +
      • CONFIG_FSP_IMAGE_ID_STRING
        • +
      +
      5. +
    5. Debug the result until port 0x80 outputs +
        +
      1. 0x90: POST_FSP_TEMP_RAM_INIT + - Just before calling + TempRamInit +
        2. +
      2. Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found
        3. +
      +
      6. +
    + + +

    Calling TempRamInit

    +

    +Use the following steps to debug the call to TempRamInit: +

    +
      +
    1. Add the CPU microcode update file +
        +
      1. Add the microcode file with the following command +
        util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin
        +
        2. +
      2. Set the Kconfig values +
          +
        • CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step
          • +
        • CONFIG_CPU_MICROCODE_CBFS_LEN
          • +
        +
        3. +
      +
      2. +
    2. Debug the result until port 0x80 outputs +
        +
      1. 0x90: POST_FSP_TEMP_RAM_INIT + - Just before calling + TempRamInit +
        2. +
      2. 0x2A - Just before calling + cache_as_ram_main + which is the start of the verstage code which may be part of romstage +
        3. +
      +
      3. +
    + +

    Modified: 31 January 2016

    diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 68a52c8c98..2b23b39e23 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -70,9 +70,62 @@
  • Get result to start booting
  • Early Debug
  • Implement and debug the bootblock code
    • +
  • Implement and debug the call to TempRamInit
    • + +
    + + + + + + + + + + + + + + + + + + + + + + + + +

    Features

    SoCWhereTesting
    Cache-as-RAM + Find + FSP binary: + cache_as_ram.inc
    + Enable: FSP 1.1 TempRamInit + called from + cache_as_ram.inc
    + Disable: FSP 1.1 TempRamExit called from + after_raminit.S
    +     		FindFSP: POST code 0x90 + (POST_FSP_TEMP_RAM_INIT) + is displayed
    + Enable: POST code + 0x2A + is displayed
    + Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit +
    FSPWhereTesting
    TempRamInitFSP TempRamInitFSP binary found: POST code 0x90 + (POST_FSP_TEMP_RAM_INIT) + is displayed
    + TempRamInit successful: POST code + 0x2A + is displayed
    +
    + + +

    Modified: 31 January 2016

    diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index e08be830ff..456db802a8 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -14,6 +14,7 @@

    1. Required Files
      2. +
    2. Add the FSP Binary File to the coreboot File System

    @@ -44,6 +45,18 @@ +

    +

    Add the FSP Binary File to coreboot File System

    +

    + Add the FSP binary to the coreboot flash image using the following command: +

    +
    util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin
    +

    + This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the + FSP code for TempRamInit may be executed in place. +

    + +

    Modified: 31 January 2016

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