From 7d25651ed3eb78228a00b479454d0ab2417f3f2a Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 20 Nov 2016 08:03:49 +0200 Subject: AGESA f14: Consolidate early P-states setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/amd/agesa/family14/fixme.c | 4 ++++ src/mainboard/amd/inagua/romstage.c | 4 ---- src/mainboard/amd/persimmon/romstage.c | 3 --- src/mainboard/amd/south_station/romstage.c | 3 --- src/mainboard/asrock/e350m1/romstage.c | 3 --- src/mainboard/elmex/pcm205400/romstage.c | 3 --- src/mainboard/gizmosphere/gizmo/romstage.c | 12 ------------ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 3 --- src/mainboard/lippert/frontrunner-af/romstage.c | 3 --- src/mainboard/lippert/toucan-af/romstage.c | 3 --- src/mainboard/pcengines/apu1/romstage.c | 3 --- 11 files changed, 4 insertions(+), 40 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index ab10e3a704..25a32bdb9c 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -98,6 +98,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + MsrReg = 0; + LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 151ce31e87..3e37e03f35 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time - */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index d553c1b52f..980ff3edbc 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5ef95a0ceb..4b725c07ab 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 6d2cad2b73..7a849e4739 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,9 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr(0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index d553c1b52f..980ff3edbc 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index e6276ff04e..1335a8fe6a 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -37,21 +37,9 @@ #include #include -#define MSR_MTRR_VARIABLE_BASE6 0x020C -#define MSR_MTRR_VARIABLE_MASK6 0x020D -#define MSR_PSTATE_CONTROL 0xC0010062 - - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - msr_t msr; - - - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - msr.lo = 0; - msr.hi = 0; - wrmsr (MSR_PSTATE_CONTROL, msr); amd_initmmio(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index ea2e11f324..5f22aaadbd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -62,9 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 0beda771ad..ccb6b39bea 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 44a27ca1ee..b2590fc216 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index cf4f3fa370..f8e6318773 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { -- cgit v1.2.3