From 7ad8b0987ac6f3438b209ce2c6d3bd16a5c93f21 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 9 May 2023 09:49:13 +0200 Subject: mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control Register With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ia8b7f997ca6234add569da751e1070144790e258 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041 Tested-by: build bot (Jenkins) Reviewed-by: Jan Samek Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index d01d547096..7362a486d0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -59,6 +60,11 @@ void variant_mainboard_final(void) if (parent && parent->device == PCI_DID_TI_XIO2001) pci_write_config8(parent, 0xd8, 0x3e); } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); } static void finalize_boot(void *unused) -- cgit v1.2.3