From 78c4d0f6a6a797742ddbd7d7dcb9a80fe2dc99d3 Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Mon, 12 Sep 2022 13:19:11 +0800 Subject: soc/intel/meteorlake: Enable tbtPcie2/3 Adding support enables/disables tbtPcie2/3 by usb4_params. BUG=b:244687646 TEST= TRP2/3 are enabled as expected. before patch [INFO ] PCI: Static device PCI: 00:07.2 not found, disabling it. [INFO ] PCI: Static device PCI: 00:07.3 not found, disabling it. after patch [DEBUG] PCI: 00:07.2 subordinate bus PCI Express [DEBUG] PCI: 00:07.2 [8086/7ec6] enabled [DEBUG] PCI: 00:07.3 subordinate bus PCI Express [DEBUG] PCI: 00:07.3 [8086/7ec7] enabled Signed-off-by: Ivy Jian Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530 Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Tarun Tuli --- src/soc/intel/meteorlake/romstage/fsp_params.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index be242e92d6..109a7443ea 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -230,6 +230,8 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssItbtPcie0En = !(config->tbt_pcie_port_disable[0]); m_cfg->TcssItbtPcie1En = !(config->tbt_pcie_port_disable[1]); + m_cfg->TcssItbtPcie2En = !(config->tbt_pcie_port_disable[2]); + m_cfg->TcssItbtPcie3En = !(config->tbt_pcie_port_disable[3]); } static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, -- cgit v1.2.3