From 7875dbd9812e2359de2c5aed7754703138878466 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 16 Jun 2018 20:01:47 +0200 Subject: cpu/intel/p4-netburst: skip caching rom on model_fxx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An unidentified combination of speculative reads and branch predictions inside WRPROT-cacheable memory can cause invalidation of cachelines and loss of stack on models based on NetBurst microarchitecture. Therefore disable WRPROT region entirely for all family F models. As an extreme example, just changing the location of a constant string passed to printk() has been witnessed to make a the boot fail early on in romstage. Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27133 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/car/p4-netburst/cache_as_ram.S | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 63ee7236ea..95ecba96bd 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -315,6 +315,18 @@ no_msr_11e: orl $CR0_CacheDisable, %eax movl %eax, %cr0 + /* + * An unidentified combination of speculative reads and branch + * predictions inside WRPROT-cacheable memory can cause invalidation + * of cachelines and loss of stack on models based on NetBurst + * microarchitecture. Therefore disable WRPROT region entirely for + * all family F models. + */ + movl $1, %eax + cpuid + cmp $0xf, %ah + je skip_cache_rom + /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -332,6 +344,8 @@ no_msr_11e: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr +skip_cache_rom: + post_code(0x2e) /* Enable cache. */ movl %cr0, %eax -- cgit v1.2.3