From 75afc79aae192629c66e0472a6f365f566be8412 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 26 Feb 2020 13:06:01 -0600 Subject: mb/51nb/x210: update devicetree - Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Improve comment for M.2-2230 USB port (BT) Parts derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/mainboard/51nb/x210/devicetree.cb | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 6bfbe1d879..ee6e5ffd59 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -99,17 +99,20 @@ chip soc/intel/skylake register "PcieRpLtrEnable[3]" = "1" register "PcieRpEnable[8]" = "1" # NVMe controller - register "PcieRpClkReqSupport[8]" = "0" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # M.2-2230 USB (BT) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) -- cgit v1.2.3