From 7261b5ade5c2035da026837afdb20a7ec1252b19 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 5 Jun 2021 15:41:09 +0300 Subject: cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/intel/model_1067x/model_1067x_init.c | 15 --------------- src/northbridge/intel/gm45/romstage.c | 3 --- src/northbridge/intel/haswell/romstage.c | 3 --- src/northbridge/intel/i945/romstage.c | 3 --- src/northbridge/intel/ironlake/romstage.c | 3 --- src/northbridge/intel/pineview/romstage.c | 3 --- src/northbridge/intel/sandybridge/romstage.c | 3 --- 7 files changed, 33 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 3e4de1fa31..33187d754e 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -12,18 +12,6 @@ #include "chip.h" -static void init_timer(void) -{ - /* Set the APIC timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) @@ -271,9 +259,6 @@ static void model_1067x_init(struct device *cpu) /* Enable the local CPU APICs */ setup_lapic(); - /* Initialize the APIC timer */ - init_timer(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a076..744c92bd70 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -42,8 +41,6 @@ void mainboard_romstage_entry(void) /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - enable_lapic(); - /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c7903e..4980f9b7ec 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ void __weak mb_late_romstage_setup(void) /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - enable_lapic(); - early_pch_init(); /* Perform some early chipset initialization required diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d62ba..0a61780cdc 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -30,8 +29,6 @@ void mainboard_romstage_entry(void) int s3resume = 0; u8 spd_map[4] = {}; - enable_lapic(); - mainboard_lpc_decode(); if (mchbar_read16(SSKPD) == 0xcafe) { diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6811..242100b800 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include "ironlake.h" @@ -27,8 +26,6 @@ void mainboard_romstage_entry(void) int s3resume = 0; u8 spd_addrmap[4] = {}; - enable_lapic(); - /* TODO, make this configurable */ ironlake_early_initialization(IRONLAKE_MOBILE); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420cc9f..a98ae99ac8 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "raminit.h" #include "pineview.h" @@ -31,8 +30,6 @@ void mainboard_romstage_entry(void) int boot_path, cbmem_was_initted; int s3resume = 0; - enable_lapic(); - /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); pineview_early_init(); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 71b8e12782..a6f626a114 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include "sandybridge.h" #include @@ -54,8 +53,6 @@ void mainboard_romstage_entry(void) if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset(); - enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); -- cgit v1.2.3